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Design of Two-Stage Fully-Integrated CMOS Power Amplifier for V-Band Applications

V-대역을 위한 완전 집적된 CMOS 이단 전력증폭기 집적회로 설계

  • Kim, Hyunjun (School of Information and Communication Engineering, Sungkyunkwan University) ;
  • Cho, Sooho (Hanwha Systems Co., Ltd.) ;
  • Oh, Sungjae (School of Information and Communication Engineering, Sungkyunkwan University) ;
  • Lim, Wonseob (School of Information and Communication Engineering, Sungkyunkwan University) ;
  • Kim, Jihoon (Samsung Electronics Co., Ltd.) ;
  • Yang, Youngoo (School of Information and Communication Engineering, Sungkyunkwan University)
  • Received : 2016.10.25
  • Accepted : 2016.12.21
  • Published : 2016.12.30

Abstract

This paper presents a V-band two-stage power amplifier integrated circuit using TSMC 65 nm CMOS process. The simple input, output, and inter-stage matching networks based on passive components are integrated. By compensating for power gain characteristics using a pre-distortion technique, the linearity of the power amplifier was improved. The implemented two-stage power amplifier showed a power gain of 10.4 dB, a saturated output power of 9.7 dBm, and an efficiency of 20.8 % with a supply voltage of 1 V at the frequency band of 58.8 GHz.

본 논문에서는 TSMC 65 nm CMOS 공정를 이용하여 V-대역 이단 전력증폭기를 설계 및 제작하였다. 수동소자를 사용한 간단한 구조의 정합회로를 구성하였고, 입력과 출력 정합회로를 모두 집적하였다. Pre-distortion 기법을 통해 전력 이득을 보상해 줌으로써 전력증폭기의 선형성을 향상시켰다. 제작된 전력증폭기는 58.8 GHz의 동작 주파수와 1 V의 동작 전압에서 10.4 dB의 전력 이득, 9.7 dBm의 출력 전력 및 20.8 %의 효율 특성을 나타내었다.

Keywords

References

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