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CMOS 이미지 센서용 NMOS-Diode eFuse OTP 설계

Design of an NMOS-Diode eFuse OTP Memory IP for CMOS Image Sensors

  • Lee, Seung-Hoon (Department of Electronic Engineering, Changwon National University) ;
  • Ha, Pan-Bong (Department of Electronic Engineering, Changwon National University) ;
  • Kim, Young-Hee (Department of Electronic Engineering, Changwon National University)
  • 투고 : 2015.12.19
  • 심사 : 2016.02.01
  • 발행 : 2016.02.29

초록

본 논문에서는 프로그램 선택 소자는 채널 폭이 큰 NMOS (N-channel MOSFET) 트랜지스터 대신 DNW (Deep N-Well) 안에 형성된 채널 폭이 작은 isolated NMOS 트랜지스터의 body인 PW (P-Well)과 source 노드인 n+ diffusion 영역 사이에 형성된 기생하는 접합 다이오드를 사용하는 NMOS-Diode eFuse OTP (One-Time Programmable) 셀을 제안하였다. 제안된 eFuse OTP 셀은 프로그램 모드에서 NMOS 트랜지스터에 형성되는 기생하는 접합 다이오드를 이용하여 eFuse를 blowing 시킨다. 그리고 읽기 모드에서는 접합 다이오드를 이용하는 것이 아니고 NMOS 트랜지스터를 이용하기 때문에 다이오드의 contact voltage 강하를 제거할 수 있으므로 '0' 데이터에 대한 센싱불량을 제거할 수 있다. 또한 읽기 모드에서 채널 폭이 작은 NMOS 트랜지스터를 이용하여 BL에 전압을 전달하므로 OTP 셀의 blowing되지 않은 eFuse를, 통해 흐르는 읽기 전류를 $100{\mu}A$ 이내로 억제하여 blowing되지 않은 eFuse가 blowing되는 문제를 해결할 수 있다.

In this paper, an NMOS-diode eFuse OTP (One-Time Programmable) memory cell is proposed using a parasitic junction diode formed between a PW (P-Well), a body of an isolated NMOS (N-channel MOSFET) transistor with the small channel width, and an n+ diffusion, a source node, in a DNW (Deep N-Well) instead of an NMOS transistor with the big channel width as a program select device. Blowing of the proposed cell is done through the parasitic junction formed in the NMOS transistor in the program mode. Sensing failures of '0' data are removed because of removed contact voltage drop of a diode since a NMOS transistor is used instead of the junction diode in the read mode. In addition, a problem of being blown for a non-blown eFuse from a read current through the corresponding eFuse OTP cell is solved by limiting the read current to less than $100{\mu}A$ since a voltage is transferred to BL by using an NMOS transistor with the small channel width in the read mode.

키워드

참고문헌

  1. J. H. Jang, L. Y. Jin, S. K. Heo, J. P. Josonen, T. W. Kim, P. B. Ha, and Y. H. Kim, "Design of Intra Oral X-ray CMOS Image Sensing," Journal of the Korea Institute of Information and Communication Engineering, vol. 16, no. 10, pp. 2237-2246, Oct. 2012. https://doi.org/10.6109/jkiice.2012.16.10.2237
  2. ICT Brief[internet]. Available: http://webzine.iitp.kr/down/vol02/brief/ICT_Brief_2015_31.pdf.
  3. J. H. Kim, J. H. Jang, L. Y. Jin, P. B. Ha, and Y. H. Kim, "Design of Low-Power OTP Memory IP and its Measurement," KIMICS, vol. 14, no. 11, pp. 2541-2547, Nov. 2010.
  4. S. H. Kulkarni, Z. Chen, B. Srinivasan, B. Pedersen, U. Bhattacharya, and K. Zhang, "Low-Voltage Metal-Fuse Technology Featuring a 1.6V-Programmable 1T1R Bit Cell with an Integrated 1V Charge Pump in 22nm Tri-Gate Process," Digest of Technical Papers, Symposium on VLSI Circuits, pp. C174-C175, June 2015.
  5. G. Uhlmann, T. Aipperspach, T. Kirihata, Chandrasekharan, Kothandaraman, Y. Z. Li, C. Paone, B. Reed, N. Robson, J. Safran, D. schmitt, and S. Iyer, "A Commercial Field-Programmable Dense eFUSE Array Memory with 99.999% Sense Yield for 45nm SOI CMOS," Digest of Technical Papers, IEEE International Solid-State Circuits Conference, pp. 406-407, Feb. 2008.
  6. J. H. Kim, D. H. Kim, L. Y. Jin, P. B. Ha, and Y. H. Kim, "Design of 1-Kb eFuse OTP memory IP with Reliability Considered," Journal of Semiconductor Technology and Science, vol. 11, no. 2, pp. 88-94, June 2011. https://doi.org/10.5573/JSTS.2011.11.2.088
  7. M. Shi, J. He, L.Zhang, C. Ma, X. Zhou, H. Lou, H. Zhuang, R. Wang, Y. Li, Y. Ma, W. Wu, W. Wang, and M. Chan, "Zero-Mask Contact Fuse for One-Time-Programmable Memory in Standard CMOS Processes," IEEE Electron Device Letters, vol. 32, no. 7, pp. 955-957, July 2011. https://doi.org/10.1109/LED.2011.2147754
  8. S. Chung, and W. K. Fang, "I-fuse: A Disruptive OTP Technology for with Excellent Manufacturability," Joint Symposium 2015 - eMDC and ISSM, Sep. 2015.
  9. S. C. Chung, Circuit and System for Using Junction Diode as Program Selector for One-Time Programmable Devices, U.S. Patent 0201749, San Jose, C.A., 2013.
  10. H. Park, S. H. Lee, M. H. Park, P. B. Ha, and Y. H. Kim, "Design of Small-Area Dual-Port eFuse OTP Memory IP for Power ICs" Journal of Korea Information, Electronics, and Communication Technology, vol. 8, no. 4, pp. 310-318, Aug. 2015. https://doi.org/10.17661/jkiiect.2015.8.4.310