참고문헌
- L. Benini and G. De Micheli, "Networks on Chips: A New SoC Paradigm," Computer, Vol. 35, No. 1, pp. 70-78, 2002. https://doi.org/10.1109/2.976921
- U. Y. Ogras, et al., "Voltage-Frequency Island Partitioning for GALS-based Networks-on-Chip," Proceedings of the 44th ACM/IEEE Design Automation Conference, pp. 110-115, 2007.
- A. Demiriz, N. Bagherzadeh, and O. Ozturk, "Voltage Island based Heterogeneous NoC Design through Constraint Programing," Computers & Electrical Engineering, Vol. 40, No. 8, pp. 307-316, 2014. https://doi.org/10.1016/j.compeleceng.2014.08.005
- S. Vangal, et al., "An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS," IEEE Journal of Solid-State Circuits, Vol. 43, No. 1, pp. 29-41, 2008. https://doi.org/10.1109/JSSC.2007.910957
- K. Goossens, J. Dielissen, and A. Radulescu, "A thereal Network on Chip: Concepts, Architectures, and Implementations," IEEE Design & Test of Computers, Vol. 22, No. 5, pp. 414-421, 2005. https://doi.org/10.1109/MDT.2005.99
- D. Abercrombie, P. Elakkumanan, and L. Liebmann "Restrictive Design Rules and Their Impact on 22 nm Design and Physical Verification," Proceedings of Electronic Design Processes Symposium, Vol. 143, 2009.
- L. E. Bechtold, D. Redman, and B. Tawfellos, "Semiconductor Reliability Using Random and Wearout Failure Models," Proceedings of Reliability and Maintainability Symposium, pp. 1-6, 2014.
- H. Kim, et al., "Use It or Lose It: Wear-out and Lifetime in Future Chip Multiprocessors," Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, pp. 136-147, 2013.
- D. Fick et al., "A Highly Resilient Routing Algorithm for Fault Tolerant NoCs," Proceedings of Design, Automation and Test in Europe, pp. 21-26, 2009.
- M. Fattah et al., "A Low-Overhead, Fully-Distributed, Guaranteed-Delivery Routing Algorithm for Faulty Network-on-Chips," Proceedings of the 9th International Symposium on Networks-on-Chip, p. 18, 2015.
- A. Vitkovskiy, V. Soteriou, and P. V. Gratz, "Wear-Aware Adaptive Routing for Networks-on-Chips," Proceedings of the 9th International Symposium on Networks-on-Chip, p. 28, 2015.
- N. Chatterjee and S. Chattopadhyay, "Fault Tolerant Mesh based Network-on-Chip Architecture," Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 417-420, 2015.
- M. E. Gomez, et al., "An Efficient Fault-Tolerant Routing Methodology for Meshes and Tori," IEEE Computer Architecture Letters, Vol. 3, Issue 1, pp. 3-3, 2004. https://doi.org/10.1109/L-CA.2004.1
- M. Valinataj, et al., "A Link Failure Aware Routing Algorithm for Networks-on-Chip in Nano Technologies," Proceedings of 9th IEEE Conference on Nanotechnology, pp. 687-690, 2009.
- C. Seiculescu, et al., "NoC Topology Synthesis for Supporting Shutdown of Voltage Islands in SoCs," Proceedings of 46th ACM/IEEE Design Automation Conference, pp. 822-825, 2009.
- S. Tosun, et al., "Fault-Tolerant Topology Generation Method for Application-Specific Network-on-Chips," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 34, No. 9, pp. 1495-1508, 2015 https://doi.org/10.1109/TCAD.2015.2413848
- E. Wachter, et al., "Topology-Agnostic Fault-Tolerant NoC Routing Method," Proceedings of Design, Automation and Test in Europe, pp. 1595-1600, 2013.
- W. Y. Jang, D. Ding, and D. Z. Pan, "A Voltage-Frequency Island Aware Energy Optimization Framework for Networks-on-Chip," Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 264-269, 2008.
- P. Ghosh and A. Sen, "Efficient Mapping and Voltage Islanding Technique for Energy Minimization in NoC under Design Constraints," Proceedings of ACM Symposium on Applied Computing, pp. 535-541, 2010.
- C. L. Li, et al., "Communication-aware custom topology generation for VFI network-on-chip," IEICE Electronics Express, Vol. 11, No. 18, pp. 1-8, 2014.
- B. Huang, et al., "Application-Specific Networkon-Chip Synthesis with Topology-Aware Floorplanning," Proceedings of 25th Symposium on Integrated Circuits and Systems Design, pp. 1-6, 2012.
- W. Liu, et al., "NoC Traffic Suite Based on Real Applications," Proceedings of IEEE Computer Society Annual Symposium on VLSI, pp. 66-71, 2011.
- A. B. Kahng, et al., "ORION 2.0: A Fast and Accurate NoC Power and Area Model for Early-Stage Design Space Exploration," Proceedings of Design, Automation and Test in Europe, pp. 423-428, 2009.
- W. J. Dally and B. Towles, "Route Packets, Not Wires: On-chip Interconnection Network," Proceedings of Design Automation Conference, pp. 684-689, 2001.
- H. Kim, et al., "Reducing Network-on-Chip Energy Consumption Through Spatial Locality Speculation," Proceedings of Fifth ACM/IEEE International Symposium on Networks-on-Chip, pp. 233-240, 2011.
- S. Park, et al., "Approaching the Theoretical Limits of a Mesh NoC with a 16-Node Chip Prototype in 45nm SOI," Proceedings of the 49th ACM/IEEE Design Automation Conference, pp. 398-405, 2012.
- S. Murali, "Designing Reliable and Efficient Networks on Chips," Springer, 2009.
- J. Han, et al., "Contention-Aware Energy Management Scheme for NoC-Based Multicore Real-Time Systems," IEEE Transactions on Parallel and Distributed Systems, Vol. 26, No. 3, pp. 691-701, 2015. https://doi.org/10.1109/TPDS.2014.2307866
피인용 문헌
- Power-efficient error-resilient network-on-chip router using selective error correction code scheme pp.1350-911X, 2018, https://doi.org/10.1049/el.2018.5389
- A joint optimization method for NoC topology generation vol.74, pp.7, 2018, https://doi.org/10.1007/s11227-018-2339-0