정보처리학회논문지:컴퓨터 및 통신 시스템 (KIPS Transactions on Computer and Communication Systems)

  • 제5권1호
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  • Pages.1-6
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  • 2016
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  • 2287-5891(pISSN)
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  • 2734-049X(eISSN)
한국정보처리학회 (Korea Information Processing Society)
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반복된 삭제/쓰기 동작에서 스트레스로 인한 Disturbance를 최소화하는 플래쉬 메모리 블록 삭제 방법

Disturbance Minimization by Stress Reduction During Erase Verify for NAND Flash Memory

  • 서주완 (SK하이닉스반도체) ;
  • 최민 (충북대학교 정보통신공학부)
  • 투고 : 2015.09.04
  • 심사 : 2016.01.09
  • 발행 : 2016.01.31
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⟨ 이전 논문 다음 논문 ⟩

초록

본 논문은 NAND Flash Memory 수명을 향상시키기 위한 동작 algorithm 개선을 제안한다. Flash memory에 대한 read/write/erase 과정에서, 해당 cell의 Vth가 원하는 level대로 위치를 한다면 문제가 없으나, 원하는 위치대비 변동이 되어 있다면 잘못된 data를 읽어내게 된다. 이러한 cell간 interference나 disturbance 현상들은 program이나 erase 동작이 반복(EW cycle)될수록 더 심해지는 특징이 있다. 이는 반복되는 high bias 인가상태에서 벌어지는 FN tunneling 현상으로 인한 tunnel oxide 막질손상(trap site 증가)에 기인한다고 알려져 있다. 본 논문에서는 erase cell 관점에서 stress양 자체를 감소시킴으로써 cell 열화 속도를 느리게 하여, 궁극적으로 발생하는 Vth 변동사항인 disturbance를 줄일 수 있는 erase 동작방법에 대해 논한다.

This paper focuses on algorithm innovation of NAND Flash Memory for enhancing cell lifetime. During flash memory read/write/erase, the voltage of a specific cell should be a valid voltage level. If not, we cannot read the data correctly. This type of interference/disturbance tends to be serious when program and erase operation will go on. This is because FN tunneling results in tunnel oxide damage due to increased trap site on repetitive high biased state. In order to resolve this problem, we make the cell degradation by reducing the amount of stress in terms of erase cell, resulting in minimizing the cell disturbance on erase verify.

키워드

참고문헌

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