A ZVS Resonant Converter with Balanced Flying Capacitors

Abstract

This paper presents a new resonant converter to achieve the soft switching of power devices. Two full-bridge converters are connected in series to clamp the voltage stress of power switches at V_in/2. Thus, power MOSFETs with a 500V voltage rating can be used for 800V input voltage applications. Two flying capacitors are connected on the AC side of the two full-bridge converters to automatically balance the two split input capacitor voltages in every switching cycle. Two resonant tanks are used in the proposed converter to share the load current and to reduce the current stress of the passive and active components. If the switching frequency is less than the series resonant frequency of the resonant tanks, the power MOSFETs can be turned on under zero voltage switching, and the rectifier diodes can be turned off under zero current switching. The switching losses on the power MOSFETs are reduced and the reverse recovery loss is improved. Experiments with a 1.5kW prototype are provided to demonstrate the performance of the proposed converter.

I. INTRODUCTION

Three-level converters or inverters have been proposed for high voltage applications such as high speed railway electrical systems [1], three-phase high power factor correction converters, ship electric power distribution systems [2], reactive power compensators [3]-[5] and AC motor systems [6]-[8]. Three-level converters/inverters [3]-[8] with a neutral-point diode clamp, a capacitor clamp or series H-bridge topologies have been proposed and developed to decrease the voltage stress of power devices and to increase the switching frequency. As a result, the size of the passive components can be decreased. For modern power converters, a compact size, high power density and high circuit efficiency are normally required. Thus, three-level converters [9]-[14] with zero voltage switching (ZVS) have been proposed to reduce the switching losses on power devices at a desired load range. Based on the resonant behavior due to the leakage inductance and resonant capacitance, the power switches can be turned on under ZVS during the transition interval. However, the ZVS range of power switches depends on the load power and input voltage conditions. Thus, it is very difficult to design a ZVS three-level converter with a wide range of load conditions. Recently, resonant converters [14]-[16] have received a lot of attention due to their essential advantages in terms of a high conversion efficiency and a wide ZVS range of the load condition. If the switching frequency is less than the series resonant frequency, the rectifier diodes at the secondary side are operated under zero current switching (ZCS) and the power switches are operated under ZVS turn-on. Thus, the reverse recovery losses of the diode rectifier are improved and the switching losses of the power switches are reduced. However, the voltage stress of the power switches in a conventional resonant converter is equal to the input voltage. In conventional three-level resonant converters [17], [18], the input split voltages cannot be balanced automatically in every switching cycle.

This paper presents a new resonant converter with the functions of a low voltage stress of the power switches, low switching losses and balanced input capacitor voltages in every switching cycle. Two full-bridge resonant converters are connected in series at the high voltage side to limit the voltage stress of the power switch at Vin/2. The secondary sides of the two full-bridge converters are connected in parallel to share the load current and to reduce the size of the active and passive components. In order to balance the two input capacitor voltages, two flying capacitors are connected between the AC sides of the two full-bridge converter legs. Thus, the input capacitor voltages can be automatically balanced in each switching cycle. Pulse frequency modulation is adopted to regulate the output voltage. The input impedance of the resonant converter is controlled as an inductive load at the switching frequency. Thus, the power switches can be turned on under ZVS with a wide range of load conditions. If the switching frequency is lower than the series resonant frequency, the rectifier diodes can be turned off under ZCS. The system analysis, circuit characteristics and a design example of the prototype circuit are discussed in detail. Finally, experiments are provided to demonstrate the performance of the proposed converter.

 

II. PROPOSED CONVERTER

Fig. 1(a) shows a block diagram of a general two-stage AC/DC converter. The front stage is a three-phase power factor corrector (PFC) to achieve a high power factor and to obtain a stable DC bus voltage Vin. The second stage is a DC/DC converter to provide a stable output voltage against load current variations. Fig. 1(b) shows a circuit diagram of a conventional three-phase bidirectional PFC. In this circuit, energy can be transferred from an AC source to a DC load or from a DC load to an AC source. The output DC voltage Vin of a three-phase PFC is normally regulated at 750V-800V. Fig. 1(c) presents a circuit diagram of the proposed new DC/DC converter. Two full-bridge resonant converters are connected in series at the high voltage side to reduce the voltage stress of the power switches and to achieve high circuit efficiency due to ZVS turn-on for each power switch. The secondary sides of these two converters are connected in parallel in order to reduce the current stress of the passive and active components. In order to automatically balance the two input split capacitor voltages vCin1 and vCin2, two flying capacitors Cf1 and Cf2 are connected at the AC terminal points (a, c) and (b, d). Thus, the two split capacitor voltages and the two flying voltages are automatically balanced, vCin1=vCin2=vCf1=vCf2=Vin/2, in a switching cycle. Cin1 and Cin2 are input split capacitances. S1-S8 are power MOSFETs. Lr1 and Lr2 are resonant inductances. Cr1 and Cr2 are resonant capacitances. C1-C8 are the output capacitances of S1-S8, respectively. D1-D4 are the rectifier diodes at the output side. Lm1 and Lm2 are the magnetizing inductances of the transformers T1 and T2, respectively. Co is output capacitance. The first resonant converter includes Cin1, S1-S4, C1-C4, Cr1, Lr1, T1, D1, D2 and Co. The components of the second resonant converter are Cin2, S5-S8, C5-C8, Cr2, Lr2, T2, D3, D4 and Co. Cf1 and Cf2 are used to balance vCin1 and vCin2 in every switching cycle. The voltage stress of each power switch is clamped at Vin/2. Therefore, MOSFETs with 500V or 600V of voltage stress can be used at the 800V input voltage condition. The pulse frequency modulation scheme is adopted to regulate the output voltage. If the switching frequency is less than the series resonant frequency at the full load and maximum input voltage case, the power switches S1-S8 are turned on at ZVS and the rectifier diodes D1-D4 are turned off at ZCS. Thus, the switching losses of the power switches are reduced and the reverse recovery losses of the rectifier diodes are improved.

Fig. 1.Circuit diagram. (a) Two-stage AC/DC converter. (b) Front stage with a general three-phase PFC. (c) Proposed ZVS DC/DC converter with two full-bridge resonant circuits and two flying capacitors.

vCin1 and vCin2 vCin1

 

III. OPERATION PRINCIPLES

In this section, the system analysis and operation principle of the proposed converter are discussed assuming the following assumptions. 1) The transformers T1 and T2 have the same magnetizing inductances Lm1=Lm2=Lm and turns ratios n=np/ns1=np/ns2, 2) S1-S8 are ideal and have the same output capacitances C1=...=C8=Coss, 3) the diodes D1-D4 areideal, 4) the resonant inductances Lr1=Lr2=Lr, 5) the resonant capacitances Cr1=Cr2=Cr, 6) Co is large enough that Vo is a constant voltage, 7) VCin1=VCin2=VCf1=VCf2=Vin/2, and 8) Cin1=Cin2 and Cf1=Cf2. Pulse frequency modulation is adopted to change the input impedance of the proposed converter so that the output voltage is regulated at a desired voltage value against different input voltage and load conditions. Based on the on/off states of S1-S8 and D1-D4, six operating modes can be derived in a switching period. Fig. 2 shows the key PWM waveforms of the proposed converter. The duty cycle of S1-S8 is 0.5. S1, S4, S5 and S8 have the same PWM waveforms. In the same manner, S2, S3, S6 and S7 have the same PWM waveforms. However, the PWM waveforms of S1 and S2 are complementary each other. The equivalent circuits of each operation mode are shown in Fig. 3. Before time t0, S1-S8, D2 and D4 are all in the off-state. The capacitors C1, C4, C5 and C8 are discharged, and C2, C3, C6 and C7 are charged.

Fig. 2.Key waveforms of the proposed converter.

Fig. 3.Operation modes of the proposed converter in one switching cycle. (a) Mode 1. (b) Mode 2. (c) Mode 3. (d) Mode 4. (e) Mode 5. (f) Mode 6.

Mode 1 [t0 - t1]: At t0, C1, C4, C5 and C8 are discharged to zero voltage. Since iLr1 and iLr2 are both negative, the anti-parallel diodes of S1, S4, S5 and S8 are conducting. Therefore, S1, S4, S5 and S8 can be turned on at this moment to achieve ZVS. The flying capacitor voltages vCf1=VCin1 and vCf2=vCin2. The voltage stresses of S2 and S3 are equal to VCin1, and the voltage stresses of S6 and S7 are equal to VCin2. In resonant circuit 1, iLr1>iLm1 and the diode D1 conducts. Thus, vLm1=nVo and iLm1 is increasing in this mode. Cr1 and Lr1 are resonant with the initial voltage Vin/2-nVo-vCr1(t0). Similarly, Cr2 and Lr2 are resonant with the initial voltage Vin/2-nVo-vCr2(t0) in the second resonant circuit, and iLm2 is also increasing. The input power is transferred to the output load through (S1, Lr1, T1, S4, D1) in resonant circuit 1 and (S5, Lr2, T2, S8, D3) resonant circuit 2. Thus, the resonant inductor currents and the capacitor voltages in this mode are expressed as:

where

Mode 2 [t1 - t2]: At t1, iLr1=iLm1 and iLr2=iLm2. Then, the diodes D1-D4 are off in this mode. Since S1 and S4 are still conducting, Cr1, Lr1 and Lm1 are resonant in resonant circuit 1. In the same manner, S5 and S8 are still conducting so that Cr2, Lr2 and Lm2 are resonant in resonant circuit 2. Thus, iLr1, iLr2, vCr1 and vCr2 are expressed as:

where

Mode 3 [t2 - t3]: At t2, S1, S4, S5 and S8 are turned off and the diodes D2 and D4 are conducting. Thus, vLm1=vLm2=-nVo. The magnetizing currents iLm1 and iLm2 decrease with a slope of -nVo/Lm. Since iLr1(t2)>0 and iLr2(t2)>0, C1, C4, C5 and C8 are charged and C2, C3, C6 and C7 are discharged.

If the energy stored in Lr1 and Lr2 at t2 is greater than the energy stored in C1-C8, then C2, C3, C6 and C7 can be discharged to zero voltage at time t3.

Mode 4 [t3 - t4]: At t3, C2, C3, C6 and C7 are discharged to zero voltage and the anti-parallel diodes of S2, S3, S6 and S7 are conducting. Before iLr1 and iLr2 become negative, S2, S3, S6 and S7 can be turned on at this moment under ZVS. Since D2 and D4 are conducting, vLm1=vLm2=-nVo. Thus, iLm1 and iLm2 decrease in this mode. The voltage stresses of S1 and S4 are equal to VCin1, and the voltage stresses of S5 and S8 are equal to VCin2. The flying capacitor voltages vCf1=VCin2 and vCf2=vCin1. In circuit module 1, Cr1 and Lr1 are resonant with the initial voltage nVo-Vin/2-vCr1(t3). Similarly, Cr2 and Lr2 are resonant with the initial voltage nVo-Vin/2-vCr2(t3) in the second resonant circuit.

The input power is transferred to the output load through S3, Lr1, T1, S2 and D2 in resonant circuit 1 and through S7, Lr2, T2, S6 and D4 in resonant circuit 2.

Mode 5 [t4 - t5]: At t4, iLr1=iLm1 and iLr2=iLm2. Thus, the diodes D1-D4 are off. Since S2, S3, S6 and S7 are still in the on-state, Cr1, Lr1 and Lm1 are resonant in circuit 1, and Cr2, Lr2 and Lm2 are resonant in circuit 2.

The flying capacitor voltages vCf1=VCin2 and vCf2=vCin1 in this mode.

Mode 6 [t5 - Ts+t0]: At t5, S2, S3, S6 and S7 are turned off and the diodes D1 and D3 are conducting. The magnetizing voltages vLm1=vLm2=nVo. Thus, iLm1 and iLm2 increase in this mode. Since iLr1 and iLr2 are negative, C1, C4, C5 and C8 are discharged and C2, C3, C6 and C7 are charged.

If the energy stored in Lr1 and Lr2 at t5 is greater than the energy stored in C1-C8, then C1, C4, C5 and C8 can be discharged to zero voltage at time Ts+t0. Then, the operating modes of the proposed converter in a switching cycle are complete.

 

IV. CONVERTER PERFORMANCE ANALYSIS

The output voltage of the proposed converter is based on pulse frequency modulation. Thus, the fundamental harmonic approach with a variable switching frequency is used to approximately analyze the steady state of the proposed converter. The power transfer from the input terminal to the output load through two full-bridge resonant tanks is depended on the switching frequency. All of the harmonics of the switching frequency are neglected in the following discussion. Fig. 4 shows an equivalent circuit of the proposed converter for the derivation of the steady state model. The equivalent circuit components in the two resonant tanks are identical. Each resonant tank is supplied one-half of the input power to the output load. Since the duty ratio of each power switch is equal to 0.5, the input AC voltages vab and vcd of the resonant tanks are square waveforms with two voltage levels Vin/2 and -Vin/2. The AC voltages vab and vcd can be expressed as the fundamental frequency term and the harmonics term.

Fig. 4.Equivalent circuit of the proposed converter for the derivation of steady state model.

From (25), the fundamental root-mean-square (rms) value of vab and vcd is equal to . Due to the on-off states of D1-D4, the fundamental rms value of the magnetizing voltages is expressed as vLm1,rms = vLm2,rms = . Since the average output current of each center-tapped rectifier is equal to Io/2, the rms value of the secondary winding currents is equal to iT1,s,rms = iT2,s,rms = . Therefore, the load resistance Ro reflected to the transformer primary side can be expressed as:

The resonant tank is excited by an effectively fundamental sinusoidal input voltage vf and it drives the effective AC resistive load Rac. The pulse frequency modulation (PFM) scheme is adopted to regulate the AC voltage gain of the proposed converter. The AC voltage gain of the resonant tank can be expressed as:

where , k=Lr/Lm, Cr1=Cr2=Cr, Lr1=Lr2=Lr and fs is the switching frequency. The DC voltage gain Gdc of the proposed converter is given as:

where Vf is the voltage drop on the rectifier diodes D1-D4. If the input and output DC voltages are given, the operating switching frequency can be obtained by Gdc=Gac.

A laboratory prototype is implemented with the following specifications: Vin=750V-800V, Vo=48V, Po=1500W and the series resonant frequency fr=120kHz. The primary and secondary winding turns of the transformers T1 and T2 are 34 turns and 4 turns, respectively. Thus, the minimum and maximum DC voltage gains of the resonant converter are expressed as:

The AC equivalent resistance Rac at the full load condition is given as:

In the prototype circuit, the selected inductance ratio of Lr and Lm is k=Lr/Lm=0.2. Based on (27), (29) and (30), the AC voltage gain curves of the proposed converter with different quality factors Q and frequency ratios F at k=0.2 are illustrated in Fig. 5. From Fig. 5, it is observed that the output voltage can be regulated if the quality factor Q ≤ 0.5 at a full load. Therefore, Q=0.5 at a full load is selected in the prototype circuit. The AC voltage gain of the proposed converter at the no load condition (Q=0) is given as:

Fig. 5.Gain curves of proposed resonant converter with Vin,min=750V and Vin,max=800V.

Therefore, the output voltage Vo can be regulated at the no load condition. Based on the derived Rac, k, Q and fr, the resonant inductances, the magnetizing inductances and the resonant capacitances can be obtained.

The voltage stress of S1-S8 is equal to Vin,max/2=400V. MOSFETs (IRFP460) with 500V/20A ratings are selected for S1-S8. The voltage stress and average current of D1-D6 are equal to 2(Vo + Vf ) = 98.2V and Io,max / 4 ≈ 7.8A , respectively. Diodes (KCU30A30) with 300V/30A ratings and a 1.1V voltage drop are adopted for D1-D4. The adopted capacitances Cin1=Cin2=470μF/450V, Cf1=Cf2=100nF/630V and Co=2200μF/100V.

 

V. EXPERIMENTAL RESULTS

Experiments with a prototype circuit, with the circuit components derived in the previous section, are provided to demonstrate the performance of the proposed converter. Fig. 6 shows the measured gate voltages of S1-S8 at a full load with the input voltage Vin=750V and 800V conditions. Fig. 7 illustrates the measured gate voltage, drain voltage and switch current of S1 at light (25%) and full (100%) loads with different input voltages. Before S1 is turned on, iS1 is negative to discharge the drain-to-source capacitor of S1. Therefore, S1 can be turned on under ZVS when the drain voltage vS1,ds is decreased to zero voltage. Since S4, S5 and S8 have the same PWM waveforms as S1, it is clear that S4, S5 and S8 are also turned on under ZVS from a 25% load to a full load. Fig. 8 shows the measured gate voltage, drain voltage and switch current of S2 at light (25%) and full (100%) loads with different input voltages. S2 is also turned on under ZVS from a 25% load to a full load. Since the PWM signals of S3, S6 and S7 are identical to the PWM signal of S2, it can be determined that S3, S6 and S7 are also turned on under ZVS. Fig. 9 gives the measured results of the gate voltages, AC terminal voltages, resonant inductor currents and resonant capacitor voltages at a full load. The two inductor currents and the two capacitor voltages are balanced under the test results. Fig. 10 gives the measured switch currents iS1 and iS2, inductor current iLr1 and flying capacitor current iCf1 at a full load. In the same manner, the measured switch currents iS1 and iS2, inductor current iLr1 and flying capacitor current iCf1 at a full load are shown in Fig. 11. When the switches S1 and S5 are in the on-state and S2 and S6 are in the off-state, the flying capacitor voltage VCf1 is equal to the input capacitor voltage VCin1 with half of a switching period. Similarly, the flying capacitor voltage VCf1=VCin2 when the switches S1 and S5 are in the off-state and S2 and S6 are in the on-state with half of a switching period. Therefore, both of the input capacitor voltages VCin1 and VCin2 are automatically balanced at Vin/2. Fig. 12 gives test results for the two input capacitor voltages vCin1 and vCin2 and the two flying capacitor voltages at the full load and 800V input voltage case. It is clear that the two input capacitor voltages vCin1 and vCin2 are balanced at 400V and vCf1=vCf2=vCin1=vCin2=Vin/2. Fig. 13 shows the measured diode currents and two circuit output currents at the full load condition. The output currents io1 and io2 are balanced. Fig. 14 shows the measured circuit efficiencies of the proposed converter under different load and input voltage conditions.

Fig. 6.Measured gate voltages of S1-S8 at full load and (a) Vin=750V (b) Vin=800V.

Fig. 7.Measured gate voltage, drain voltage and switch current of S1 at (a) 25% load and Vin=750V (b) 25% load and Vin=800V(c) 100% load and Vin=750V(d) 100% load and Vin=800V.

Fig. 8.Measured gate voltage, drain voltage and switch current of S2 at (a) 25% load and Vin=750V (b) 25% load and Vin=800V(c) 100% load and Vin=750V(d) 100% load and Vin=800V.

Fig. 9.Measured results of the gate voltages vS1,gs and vS2,gs, AC terminal voltages vab and vcd, resonant inductor currents iLr1 and iLr2, and resonant capacitor voltages vCr1 and vCr2 at full load.

Fig. 10.Measured switch currents iS1 and iS2, inductor current iLr1 and flying capacitor current iCf1 at full load.

Fig. 11.Measured switch currents iS3 and iS4, inductor current iLr1 and flying capacitor current iCf2 at full load.

Fig. 12.Measured results of input capacitor voltages and flying capacitor voltages at full load and 800V input voltage case.

Fig. 13.Measured diode currents and two circuit output currents at full load condition.

Fig. 14.Measured efficiencies of the proposed converter with different input terminal voltages and load conditions.

 

VI. CONCLUSION

This paper presents a new full-bridge resonant converter with the characteristics of low voltages stress MOSFETs, ZVS turn-on for the MOSFETs, no reverse recovery current on the rectifier diodes, balanced two input capacitor voltages and high circuit efficiency. Two half-bridge converter legs with two spilt capacitors are adopted to reduce the voltage stress of the MOSFETs at Vin/2. Therefore, the proposed converter is suitable for use in high input voltage applications. The two flying capacitors Cf1 and Cf2 are used to automatically balance the two input capacitor voltages in every switching cycle. The two resonant circuits are used to increase the load power and to achieve ZVS for all of the power semiconductors. The system analysis, a design example and experiments are presented to demonstrate the effectiveness of the proposed converter.