전자공학회논문지 (Journal of the Institute of Electronics and Information Engineers)

  • 제52권8호
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  • Pages.40-48
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  • 2015
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  • 2287-5026(pISSN)
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  • 2288-159X(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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다중 입력 다중 출력 통신 시스템을 위한 저 복잡도의 Joint QR decomposition-Lattice Reduction 프로세서

A Low-Complexity Processor for Joint QR decomposition and Lattice Reduction for MIMO Systems

  • 박민우 (한국항공대학교 항공전자정보공학부) ;
  • 이상우 (한국항공대학교 항공전자정보공학부) ;
  • 김태환 (한국항공대학교 항공전자정보공학부)
  • Park, Min-Woo (School of Electronics and Information Engineering, Korea Aerospace University) ;
  • Lee, Sang-Woo (School of Electronics and Information Engineering, Korea Aerospace University) ;
  • Kim, Tae-Hwan (School of Electronics and Information Engineering, Korea Aerospace University)
  • 투고 : 2015.04.21
  • 심사 : 2015.07.28
  • 발행 : 2015.08.25
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⟨ 이전 논문 다음 논문 ⟩

초록

본 논문에서는 다중 입력 다중 출력 시스템을 위한 전 처리 과정인 QR Decomposition (QRD) 과 Lattice Reduction (LR)에 대하여, 두 과정의 연산의 공유성을 바탕으로 이를 공동으로 처리하는 프로세서를 제안한다. 제안하는 전 처리 프로세서는 다중 사이클 아키텍처로 설계하여 하드웨어 복잡도를 낮추었고, 두 전 처리 과정을 채널 환경에 따라 선택적으로 수행한다. 제안하는 전 처리 프로세서는 $0.18-{\mu}m$ CMOS공정의 셀 라이브러리를 사용하여 139K의 논리 게이트로 구현되었고, 최대 117MHz의 동작주파수에서 $8{\times}8$ 행렬에 대한 QRD와 LR의 수행에 대하여 $5{\mu}s$의 latency를 갖는다.

This paper presents a processor that performs QR decomposition (QRD) as well as Lattice Reduction (LR) for multiple-input multiple-output (MIMO) systems. By sharing the operations commonly required in QRD and LR, the hardware complexity of the proposed processor is reduced significantly. In addition, the proposed processor is designed based on a multi-cycle architecture so as to reduce the hardware complexity. The proposed processor is implemented with 139k logic gates in a $0.18-{\mu}m$ CMOS process, and its latency is $5{\mu}s$ for $8{\times}8$ MIMO preprocessing both QRD and LR where the operating frequency is 117MHz.

키워드

참고문헌

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