JSTS:Journal of Semiconductor Technology and Science

  • 제15권3호
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  • Pages.423-426
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  • 2015
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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Multi-operation-based Constrained Random Verification for On-Chip Memory

  • Son, Hyeonuk (Department of Electrical and Electronic Engineering, Yonsei University) ;
  • Jang, Jaewon (Department of Electrical and Electronic Engineering, Yonsei University) ;
  • Kim, Heetae (Department of Electrical and Electronic Engineering, Yonsei University) ;
  • Kang, Sungho (Department of Electrical and Electronic Engineering, Yonsei University)
  • 투고 : 2015.03.21
  • 심사 : 2015.05.31
  • 발행 : 2015.06.30
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초록

Current verification methods for on-chip memory have been implemented using coverpoints that are generated based on a single operation. These coverpoints cannot consider the influence of other memory banks in a busy state. In this paper, we propose a method in which the coverpoints account for all operations executed on different memory banks. In addition, a new constrained random vector generation method is proposed to reduce the required random vectors for the multi-operation-based coverpoints. The simulation results on NAND flash memory show 100% coverage with 496,541 constrained random vectors indicating a reduction of 96.4% compared with conventional random vectors.

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참고문헌

  1. N. Kichen and A. Kuehlmann, "Stimulus Generation for Constrained Random Simulation," International Conference on Computer Aided Design (ICCAD), pp. 258-265, Nov. 2007.
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  4. M. Kudlugi, C. Sevidge and R. Tessier, "Static Scheduling of Multi-Domain Memories For Functional Verification," International Conference on Computer Aided Design (ICCAD), pp. 2-9, Nov. 2001.