JSTS:Journal of Semiconductor Technology and Science

  • 제15권3호
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  • Pages.427-435
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  • 2015
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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High-Throughput Low-Complexity Successive-Cancellation Polar Decoder Architecture using One's Complement Scheme

  • Kim, Cheolho (Dept. of Information and Communication Engr. Inha University) ;
  • Yun, Haram (Dept. of Information and Communication Engr. Inha University) ;
  • Ajaz, Sabooh (Dept. of Information and Communication Engr. Inha University) ;
  • Lee, Hanho (Dept. of Information and Communication Engr. Inha University)
  • 투고 : 2014.10.15
  • 심사 : 2015.05.28
  • 발행 : 2015.06.30
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초록

This paper presents a high-throughput low-complexity decoder architecture and design technique to implement successive-cancellation (SC) polar decoding. A novel merged processing element with a one's complement scheme, a main frame with optimal internal word length, and optimized feedback part architecture are proposed. Generally, a polar decoder uses a two's complement scheme in merged processing elements, in which a conversion between two's complement and sign-magnitude requires an adder. However, the novel merged processing elements do not require an adder. Moreover, in order to reduce hardware complexity, optimized main frame and feedback part approaches are also presented. A (1024, 512) SC polar decoder was designed and implemented using 40-nm CMOS standard cell technology. Synthesis results show that the proposed SC polar decoder can lead to a 13% reduction in hardware complexity and a higher clock speed compared to conventional decoders.

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참고문헌

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