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Extraction of Average Interface Trap Density using Capacitance-Voltage Characteristic at SiGe p-FinFET and Verification using Terman's Method

SiGe p-FinFET의 C-V 특성을 이용한 평균 계면 결함 밀도 추출과 Terman의 방법을 이용한 검증

  • Kim, Hyunsoo (School of Electrical Engineering and Computer Science, Seoul National University) ;
  • Seo, Youngsoo (School of Electrical Engineering and Computer Science, Seoul National University) ;
  • Shin, Hyungcheol (School of Electrical Engineering and Computer Science, Seoul National University)
  • 김현수 (서울대학교 전기.정보공학부) ;
  • 서영수 (서울대학교 전기.정보공학부) ;
  • 신형철 (서울대학교 전기.정보공학부)
  • Received : 2014.12.11
  • Accepted : 2015.03.30
  • Published : 2015.04.25

Abstract

Ideal and stretch-out C-V curve were shown at high frequency using SiGe p-FinFET simulation. Average interface trap density can be extracted by the difference of voltage axis on ideal and stretch-out C-V curve. Also, interface trap density(Dit) was extracted by Terman's method that uses the same stretch-out of C-V curve with interface trap characteristic, and average interface trap density was calculated at same energy level. Comparing the average interface trap density, which was found by method using difference of voltage, with Terman's method, it was verified that the two methods almost had the same average interface trap density.

고주파에서 이상적인 커패시턴스-전압 곡선과 결함이 존재하여 늘어진 커패시턴스-전압 곡선을 SiGe p-FinFET 시뮬레이션을 이용하여 보였다. 두 곡선이 게이트 전압 축으로 늘어진 전압 차이를 이용하여 평균적인 계면 결함 밀도를 구할 수 있었다. 또한 같은 특성을 이용하는 Terman의 방법으로 에너지에 따른 계면 결함 밀도를 추출하고, 동일한 에너지 구간에서 평균값을 구하였다. 전압 차이로 구한 평균 계면 결함 밀도를 Terman의 방법으로 구한 평균값과 비교하여, 두 방법의 결과가 거의 비슷한 평균 계면 결함 밀도를 나타낸다는 것을 검증하였다.

Keywords

References

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