JSTS:Journal of Semiconductor Technology and Science

  • 제15권2호
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  • Pages.177-183
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  • 2015
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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A VLSI Design for Scalable High-Speed Digital Winner-Take-All Circuit

  • Yoon, Myungchul (Department of Electronics Engineering, Dankook University)
  • 투고 : 2014.10.30
  • 심사 : 2015.01.02
  • 발행 : 2015.04.30
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초록

A high speed VLSI digital Winner-Take-All (WTA) circuit called simultaneous digital WTA (SDWTA) circuit is presented in this paper. A minimized comparison-cell (w-cell) is developed to reduce the size and to achieve high-speed. The w-cell which is suitable for VLSI implementation consists of only four transistors. With a minimized comparison-cell structure SDWTA can compare thousands of data simultaneously. SDWTA is scalable with O(mlog n) time-complexity for n of m-bit data. According to simulations, it takes 16.5 ns with $1.2V-0.13{\mu}m$ process technology in finding a winner among 1024 of 16-bit data.

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참고문헌

  1. M. A. G. Andreou, K. A. Boahen, A. Pavasovic, P. O. Pouliquen, R. E. Jenkins, and K. Strohbehn, "Current-mode subthreshold MOS circuits for analog VLSI neural systems", IEEE Trans. Neural Netw., vol. 2, no. 2, pp.205-213 1991. https://doi.org/10.1109/72.80331
  2. R. Kalim and D. M. Wilson, "Semi-parallel rankorder filtering in analog VLSI", Proc. IEEE ISCAS'99, vol. 2, pp.232-235 1999.
  3. M. Rahman, K. L. Baishnab, and F. A. Talukdar, "A high speed and high resolution VLSI Winnertake- all circuit for neural networks and fuzzy systems" IEEE ISSCC2009, pp. 1-4, 2009.
  4. J. Lazzaro, S. Ryckebusch, M. A. Mahowald, and C. A. Mead, D. S. Touretzky, Winner-Take-All Networks of O(n) Complexity, vol. 1, pp.703-711 1989 :Morgan Kaufmann.
  5. J. A. Startzyk and X. Fang, "CMOS current-mode winner-take-all circuit with both excitatory and inhibitory feedback", Electron. Lett., vol. 29, no. 10, pp.908-910 1993. https://doi.org/10.1049/el:19930606
  6. S. P. DeWeerth and T. G. Morris, "CMOS currentmode winner-take-all circuit with distributed hysteresis", Electron. Lett., vol. 31, no. 13, pp.1051-1053 1995. https://doi.org/10.1049/el:19950729
  7. G. Indiveri, "A current-mode hysteretic winnertake- all network, with excitatory and inhibitory coupling", Analog Integr. Circuits Signal Process., vol. 28, pp.279-291 2001. https://doi.org/10.1023/A:1011208127849
  8. D. Moro-Frias, M. T. Sanz-Pascual, and C. A. de La Cruz-Blas, "A novel current-mode Winner-Take-All topology," Circuit Theory and Design (ECCTD), 2011 20th European Conference on, vol., no., pp.134,137, 29-31 Aug. 2011.
  9. N. Kumar, P.O.Pouliquen, and A. G. Andreou, "Device mismatch limitations on the performance of a Hamming distance classifier" in Proc. 1993 IEEE Int. Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 327-334 1993.
  10. P. V. Tymoshchuk, and M. P. Tymoshchuk, "Stability and convergence analysis of model state variable trajectories of analogue KWTA neural circuit," Direct and Inverse Problems of Electromagnetic and Acoustic Wave Theory (DIPED), 2011 XVth International Seminar/Workshop on, vol., no., pp.26,35, 26-29 Sept. 2011.
  11. K. Uchimura, Fish, A. Milrud, V. Yadid-Pecht, O., "A high- speed digital neural network chip with low-power chain-reaction architecture," IEEE J. Solid State Circuits,, vol. 27, no.12, pp. 1862-1867, 1992. https://doi.org/10.1109/4.173116
  12. A. Schmid, Y. Leblebici, and D. Mlynek, "Mixed analogue-digital artificial-neural-network architecture with on-chip learning", IEE Proc. Circuits Devices syst., vol. 146, no. 6, pp.345-349 1999. https://doi.org/10.1049/ip-cds:19990685
  13. M. A. Abedin, Y. Tanaka, A. Ahmadi, T. Koide, and H. J. Mattausch, "Fully Parallel Associative Memory Architecture with Mixed Digital-Analog Match Circuit for Nearest Euclidean Distance Search" IEEE APCCAS2006, pp. 1309-1312, 2006.
  14. J. Kim, K. Hwang, and W. Sung, "X1000 real-time phoneme recognition VLSI using fee-forward deep neural networks," IEEE ICASS7, pp. 7510-7514, 2014.
  15. A. Kapralski, "The maximum and minimum selector SELRAM and its application for developing fast sorting machines," Computers, IEEE Transactions on, vol. 38, no. 11, pp. 1572-1577, Nov 1989. https://doi.org/10.1109/12.42127
  16. The MOSIS Service, http://www.mosis.com/ [Online]
  17. M. Ogawa, K. Ito, and T. Shibata, "A generalpurpose vector-quantization processor employing two-dimensional bit-propagating winner-take-all" IEEE Sym. VLSI Circuits Digest of Tech. Papers, vol. 35, no.11, pp. 244-247, 2002.
  18. C. K. Kwon, and K. Lee, "Highly parallel and energy-efficient exhaustive minimum distance search engine using hybrid digital/analog circuit techiquies," VLSI Systems, IEEE Transactions on, vol. 9, no. 5, pp. 726-729, 2001. https://doi.org/10.1109/92.953505
  19. J. Kim, K. Hwang, and W. Sung, "32x32 winnertake- all matrix with single winner selection," Electronics Letters, vol. 46, no. 5, pp. 333-335, 2010. https://doi.org/10.1049/el.2010.1963
  20. A. Fish, A. Milrud, V. Yadid-Pecht, O., "Highspeed and high-precision current winner-take-all circuit," Circuits and Systems II: Express Briefs, IEEE Transactions on, vol. 52, no. 3, pp. 131-135, March 2005. https://doi.org/10.1109/TCSII.2004.842062

피인용 문헌

  1. Winner-take-all in a phase oscillator system with adaptation vol.8, pp.1, 2018, https://doi.org/10.1038/s41598-017-18666-3