Medium Voltage Resonant Converter with Balanced Input Capacitor Voltages and Output Diode Currents

Abstract

This paper presents a 1.92 kW resonant converter for medium voltage applications that uses low voltage stress MOSFETs (500V) to achieve zero voltage switching (ZVS) turn-on. In the proposed converter, four MOSFETs are connected in series to limit the voltage stress of the power switches at half of the input voltage. In addition, three resonant circuits are adopted to share the load current and to reduce the current stress of the passive components. Furthermore, the transformer primary and secondary windings are connected in series to balance the output diode currents for medium power applications. Split capacitors are adopted in each resonant circuit to reduce the current stress of the resonant capacitors. Two balance capacitors are also used to automatically balance the input capacitor voltage in every switching cycle. Based on the circuit characteristics of the resonant converter, the MOSFETs are turned on under ZVS. If the switching frequency is less than the series resonant frequency, the rectifier diodes can be turned off under zero current switching (ZCS). Experimental results from a prototype with a 750-800 V input and a 48V/40A output are provided to verify the theoretical analysis and the effectiveness of the proposed converter.

I. I NTRODUCTION

Full-bridge converters with a simple structure, constant frequency pulse-width modulation and soft switching turn-on [1]-[4] have been adopted in medium power applications. However, power switches should suffer the input voltage due to the full-bridge structure. High input DC/DC converters have been developed for ship electric power distribution systems [5], three-phase AC/DC converters and the traction systems for light trains [6]-[7]. Three-level DC/DC converters [8]-[10] with low voltage and current stresses were presented to reduce the voltage stress on active switches. However, the power switches are operated at hard switching. High switching losses on the power switches reduce the circuit efficiency. In order to achieve soft switching and reduce switching losses, three-level zero voltage switching (ZVS) converters for high input voltage applications were proposed in [11]-[14]. In [13], four power switches with Vin/2 voltage stress and two power switches with Vin voltage stress are used in the three-level ZVS hybrid full bridge converter. The drawback of this circuit is that two power switches with high voltage stress are used in this converter. Resonant converters [15]-[18] have been proposed for the advantages of high conversion efficiency and high power density. Power switches are turned on under ZVS from low load to full load. If the switching frequency is less than the series resonant frequency, the rectifier diodes at output side are turned off under zero current switching (ZCS). The series-parallel connection techniques have been discussed in [19]-[21]. In [19], two transformers are adopted in three-level converter with current double rectifier for medium voltage application. However, the high current rating of rectifier diodes and large size of filter inductors are needed in this circuit topology for high load current application. The circuit efficiency will be drop at light load due to the high circulating current in conventional three-level PWM converter. The input split capacitor voltages cannot be automatically balanced. An active clamp forward converter with parallel connection in primary side was presented in [20] to achieve soft switching. However, this circuit topology cannot be used for medium voltage applications due to its high voltage stress on the power switches. A three-level resonant converter with duty cycle control has been presented in [21] to have ZVS turn-on for all of the power switches and ZCS turn-off for all of the rectifier diodes. The output currents of the two secondary sides are automatically balanced due to the series connection of the transformers. However, the input split capacitor voltages cannot be balanced automatically and the duty cycle is decreased under a light load case. Thus, the circuit efficiency under a light load is decreased.

A ZVS DC/DC converter for high input voltage and load current applications is studied in this paper. Two half-bridge legs with split capacitors are connected in series at the high voltage side to clamp the voltage stress of the power switches at half of the input voltage. Two balance capacitors are used between the AC sides of the two half-bridge legs to automatically balance the input split capacitor voltages. Three resonant circuits are used at the high voltage side in order to reduce the current stress of the resonant components. The secondary windings of the transformers are connected in series to automatically balance the output diode currents. Since the input impedance of the resonant tank is an inductive load at the switching frequency, the power switches are turned on under ZVS. As a result, the switching losses on the power switches are reduced. Finally, experiments from a 750-800 Vin put and 48V/40A output prototype were provided to verify the performance of the proposed converter.

 

II. PROPOSED CONVERTER AND OPERATION PRINCIPLE

For three-phase power factor corrector converters with a 380V or 480V utility voltage or a DC traction system, the input voltage of the DC/DC converter is equal to or higher than 750V. Fig. 1 gives the circuit topology of the proposed converter for medium voltage applications. The circuit components at the high voltage side include the input voltage Vin, power MOSFETs S1-S4 with their body diodes and parallel capacitors Coss1-Coss4, resonant capacitors Cr1-Cr6, resonant inductors Lr1-Lr3, and transformers T1 - T4. Two center-tapped rectifiers are used at the low voltage side to share the load current and to reduce the current stress of the passive components. The secondary windings of T1 and T3 are connected in series so that the primary currents iLr1 and iLr3 are balanced. Similarly, the primary currents iLr2 and iLr3 are balanced since the secondary windings of T2 and T4 are connected in series. Thus, the primary and secondary winding currents of T1-T4 are balanced. (S1 and S3) and (S2 and S4) have the same PWM waveforms with a 0.5 duty cycle. However, the driving signals of S2 and S4 are complementary with the driving signals of S1 and S3 with a short dead time. The components S1-S4 and Cr1-Cr6 establish a switched capacitor circuit [22]. Therefore, the input capacitor voltages are balanced, vCr1 +vCr2=vCr3+vCr4 =vCr5 +vCr6=Vin/2. The proposed converter includes three resonant circuits at the high voltage side. A variable frequency scheme is adopted to regulate the output voltage.

Fig. 1.Circuit configuration of the proposed converter.

The following assumptions are presumed to simplify the system analysis of the three resonant circuits. The transformers T1-T4 have the magnetizing inductances Lm1=Lm2=2Lm3=2Lm4=Lm and the turns ratios n1=n2=2n3=2n4=n. The resonant capacitances are Cr1=Cr2= Cr3 =Cr4=Cr5=Cr6 =Cr. The resonant inductances are identical Lr1 =Lr2 =Lr3 =Lr. The power MOSFETs S1-S4 have the same output capacitances Coss1=Coss2 =Coss3 =Coss4=Coss. The capacitor voltages vCr1 +vCr2=vCr3 +vCr4 =vCr5+vCr6 =Vin/2. If the switching frequency fsw is less than the series resonant frequency fr, there are six operating modes in a switching cycle. The main PWM waveforms of the proposed converter under fsw < fr are shown in Fig. 2 and Fig. 3. They give the corresponding equivalent circuit for each operation mode. If the switching frequency fsw > fr, then the resonant circuit has only four operation modes (modes 1, 3, 4 and 6) in a switching cycle. In the following statements, the six modes of operation are discussed in each switching cycle. Before time t0, S1-S4, D2 and D4 are in the off-state. Coss1 and Coss3 are discharged, and Coss2 and Coss4 are charged.

Fig. 2.Key waveforms of the proposed converter.

Fig. 3.Operation modes of the proposed converter in a switching cycle. (a) Mode 1. (b) Mode 2. (c) Mode 3. (d) Mode 4. (e) Mode 5. (f) Mode 6.

Mode 1 [t0 - t1]: Mode 1 starts at time t0 when Coss1 and Coss3 are discharged to zero voltage. Since iLr1 (t0)<0, iLr2 (t0)<0 and iLr3 (t0)<0, the anti-parallel diodes of S1 and S3 are conducting. Thus, S1 and S3 are turned on at this moment under ZVS. The voltage stresses of S2 and S4 are equal to vCr1+vCr2 and vCr3+vCr4, respectively. In this mode, the capacitor voltage vCr5+vCr6 =vCr1+vCr2. On the other hand, the capacitor voltage vCr5+vCr6 =vCr3+vCr4 in mode 3. Thus, it can be obtained that vCr1+vCr2 =vCr3+vCr4 =vCr5+vCr6 =Vin/2 in steady state. Since iLr1 > iLm1, iLr2 > iLm2 and iLr3 > iLm3, diodes D1 and D3 are conducting. In this mode, vLm1 - vLm4 are positive and iLm1 - iLm5 increase. In addition, Lr1, Cr1 and Cr2 are resonant in circuit 1; Lr2, Cr3 and Cr4 are resonant in circuit 2; Lr3, Cr5 and Cr6 are resonant in circuit 3; and power is transferred from the input voltage Vin to the output load Ro. The resonant frequency is

Mode 2 [t1 - t2]: At time t1, iLr1 (t1)=iLm1 (t1), iLr2 (t1)=iLm2 (t1) and iLr3 (t1)=iLm3 (t1)=iLm4 (t1). Thus, diodes D1-D4 are all in the off-state. In this mode, Lr1, Lm1, Cr1 and Cr2 are resonant in circuit 1; Lr2, Lm2, Cr3 and Cr4 are resonant in circuit 2; and Lr3, Lm3, Lm4, Cr5 and Cr6 are resonant in circuit 3. The resonant frequency is

Mode 3 [t2 - t3]: At time t2, S1 and S3 are turned off. Diodes D2 and D4 are conducting, vLm1-vLm4 are negative, and iLm1-iLm4 decrease. Since iLr1 (t2)>0, iLr2 (t2)>0 and iLr3 (t2)>0, Coss1 and Coss3 are charged and Coss2 and Coss4 are discharged. Coss2 and Coss4 can be discharged to zero voltage if the energy stored in Lr1 - Lr3 at t2 is greater than the energy stored in Coss1 - Coss4.

Mode 4 [t3 - t4]: At time t3, vCoss2=vCoss4=0. Since iLr1 (t3)>0, iLr2 (t3)>0 and iLr3 (t3)>0, the anti-parallel diodes of S2 and S4 are conducting. S2 and S4 can be turned on at this moment under ZVS. In mode 4, D2 and D4 are conducting, iLm1-iLm4 decrease. In addition, vCoss1=vCr1 +vCr2, vCoss3=vCr3+vCr4, and vCr5+vCr6=vCr3 +vCr4. Lr1, Cr1 and Cr2 are resonant in circuit 1; Lr2 , Cr3 and Cr4 are resonant in circuit 2; Lr3, Cr5 and Cr6 are resonant in circuit 3; and power is transferred from the input voltage Vin to the output load Ro. The resonant frequency is

Mode 5 [t4 - t5]: At time t4, iLr1 (t4)=iLm1 (t4), iLr2 (t4)=iLm2 (t4) and iLr3 (t4)=iLm3 (t4)=iLm4 (t4). Diodes D1-D4 are all in the off-state. Lr1, Lm1, Cr1 and Cr2 are resonant in circuit 1; Lr2, Lm2, Cr3 and Cr4 are resonant in circuit 2; Lr3, Lm3, Lm4, Cr5 and Cr6 are resonant in circuit 3; and the resonant frequency is

Mode 6 [t5 - T+t0]: At time t5, S2 and S4 are turned off. Diodes D1 and D3 are conducting. The magnetizing voltages vLm1-vLm4 are positive and the magnetizing currents iLm1-iLm4 increase. Since iLr1 (t5)<0, iLr2 (t5)<0 and iLr3 (t5)<0, Coss1 and Coss3 are discharged and Coss2 and Coss4 are charged. Coss1 and Coss3 can be discharged to zero voltage if the energy stored in Lr1 - Lr3 at t5 is greater than the energy stored in Coss1 - Coss4. Then, the operating modes of the proposed converter in a switching period are completed.

 

III. CONVERTER PERFORMANCE ANALYSIS AND DESIGN EXAMPLE

Three resonant circuits are included in the proposed converter to share the load power. The power transferred through the three resonant circuits is a function of the switching frequency. The input terminal of the resonant circuit is a square wave voltage. If the bandwidth of the resonant circuit is less than the switching frequency, the harmonics of the input square wave voltage can be neglected at the output terminal. The secondary side currents iD1 +iD2 and iD3 +iD4 are quasi-sinusoidal currents. If the primary inductor currents are greater than the magnetizing currents, then diodes D1 and D3 are conducting and vLm1 =vLm2 =nVo/2 and vLm3 =vLm4 =nVo/4. On the other hand, vLm1 =vLm2 =-nVo/2, vLm3 =vLm4 =-nVo/4 and rectifier diodes D2 and D4 are conducting when the primary inductor currents are less than the magnetizing currents. Since the charge/discharge time of output capacitors Coss1-Coss4 in modes 3 and 6 and the time intervals in modes 2 and 5 are much less than the time intervals in modes 1 and 4, the magnetizing inductor voltages vLm1-vLm4 approximate quasi-square waveforms.

where θm is the phase angle of the m-th harmonic frequency. The peak secondary winding currents are given as:

Thus, the load resistance Ro reflected to the transformer primary sides is shown as:

Fig. 4 shows the AC resonant circuits excited by the effective sinusoidal input voltage and the effective resistive loads Rac,1-Rac,4. The input impedances Zin,1-Zin,3 of the resonant circuits are expressed as:

Fig. 4.Equivalent circuit of the proposed converter for the derivation of steady state model.

The frequency modulation (FM) approach is adopted to regulate the AC voltage gain of the resonant circuit. The AC voltage gain of the resonant circuit is approximately expressed as:

where k=Lr/Lm and fs is the switching frequency. The DC voltage gain Gdc of the proposed converter is given as Gdc = 2nVo/Vin. The AC voltage gain at the no-load condition (Q=0) and fs=∞ is given as |Gac(f)|NLfs=∞=1/(1+k). In order to regulate the output voltage from no-load to full load, the minimum DC voltage gain must be greater than the AC voltage gain at the no-load condition. Thus, the minimum turns ratio of transformers T1 and T2 is given in (9).

A design example of the prototype circuit is provided in order to verify the system analysis of the proposed converter. A laboratory prototype was constructed to verify the effectiveness of the proposed converter. The electric specifications are Vin =750-800 V, Vo =48 V, and Io,rated =40 A. The selected series resonant frequency fr is 120 kHz. The selected inductance ratio Lm /Lr =1/k=7.

A. Turns Ratio of T1-T4

In the prototype circuit, the DC voltage gain is equal to Gdc=2nVo/Vin. Thus, the minimum turns ratio is given as n=Gdc,minVin,micdc/(2Vo) If the minimum DC voltage gain is selected as unity at the series resonant frequency, then the turns ratio of T1-T4 is given as:

The actual primary and secondary turns used in T1-T4 are np,T1=np,T2=66 turns, ns,T1=ns,T1=8 turns, np,T3=ns,T4=33 turns and ns,T3=ns,T4=8 turns. The actual turns ratios of T1 and T2 are 8.25, and the turns ratios of T3 and T4 are 4.125.

B. DC Voltage Gain of the Proposed Converter

Based on the selected turns ratio of T1-T4, the minimum and maximum DC voltage gains of the proposed converter are derived as:

C. Q Value at Full Load and AC Equivalent Resistance

Fig. 5 gives the AC voltage gain versus the frequency ratio fs/fr with k=1/7. Since the minimum and maximum DC gains are 0.99 and 1.056, respectively, the maximum Q at a full load should be less than 0.4 in order to effectively regulate the output voltage. In this prototype, the Q value at a full load is selected as 0.4. Based on (4) and (5), the AC equivalent resistances Rac,1-Rac,4 at a full load are derived as:

Fig. 5.AC voltage gain and DC voltage gain at different frequency ratio fs/fr.

D. Resonant Capacitances and Inductances

Since the resonant capacitances Cr1-Cr6 and inductances Lr1-Lr3are obtained as:

The magnetizing inductances of T1-T4 are expressed as:

E. Power Semiconductors

The input maximum voltage is 800 V and the voltage stresses of S1-S4 are equal to Vin/2=400 V. Power MOSFETs (IRFP460) with a 500 V voltage rating and a 13 A current rating at 100℃ are used for power switches S1-S4. The output voltage is 48 V and the load current is 40 A. The average currents of D1-D4 are equal to 40 A/4=10 A. The voltage stresses of D1-D4 are equal to 2Vo=96 V. Fast recovery diodes (KCU30A20) with a 200 V voltage rating and a 30 A current rating are adopted for D1-D4 in the prototype circuit.

 

IV. EXPERIMENTAL RESULTS

Based on the derived circuit parameters in the previous section, experimental verification is provided to demonstrate the performance of the proposed circuit. The measured PWM waveforms of S1-S4 at different input voltages and load conditions are given in Fig. 6. S1 and S3 have the same PWM waveforms, and S2 and S4 have identical PWM signals. However, the PWM signals of S1 and S2 are complementary each other to avoid short circuits at each half-bridge leg. At the same load power, the switching frequency at a low input voltage Vin =750 V is less than the switching frequency at a high input voltage Vin =800 V. At the same input voltage, Vin =800 V, the switching frequency at a full load is less than the switching frequency at a light load. Fig. 7 gives the measured switching frequency of the proposed converter at different input voltages and load conditions. The measured waveforms of the gate voltage and drain voltage of S1 and S2 at different input voltages and load conditions are illustrated in Fig. 8. In the same manner, Fig. 9 gives the test results of the gate voltage and drain voltage of S3 and S4 at different input voltages and load conditions. Before S1-S4 are turned on, the drain voltages are decreased to zero voltage. Therefore, the ZVS turn-on of S1-S4 is achieved. Fig. 10 shows the test waveforms of iLr1-iLr3 at a full load and different input voltages. It is clear that inductor currents iLr1 and iLr2 are balanced. Fig. 11(a) shows the test waveforms of vCr1-vCr6 at a full load and Vin=750 V. It is clear that vCr1, vCr3 and vCr6 have the same voltage waveforms and that the voltage waveforms of vCr2, vCr4 and vCr5 are balanced. Fig. 11(b) shows the test results of vCr1 +vCr2, vCr3+vC4 and vCr5 +vCr6. From the test results in Fig. 11(b), it can be seen that the three voltages vCr1+vCr2, vCr3+vCr4 and vCr5+vCr6 are balanced. In the same manner, the measured voltages vCr1-vCr6, vCr1+vCr2, vCr3+vCr4 and vCr5+vCr6 at Vin =800 V are shown in Fig. 12. Fig. 13 shows the measured gate voltage vS1,gs and the output diode currents iD1-iD4 at a full load and different input voltages. The diode currents iD1 and iD3 are balanced, and iD2 and iD4 are also balanced. The measured circuit efficiencies at different loads are shown in Fig. 14. The measured efficiency is greater than 92% from a 25% load to a full load.

Fig. 6.Measured PWM waveforms of S1-S4 at (a) Vin=750 V and 25% load. (b) Vin=750 V and 100% load. (c) Vin=800 V and 25% load. (d) Vin=800 V and 100% load.

Fig. 7.Measured switching frequencies at different input voltages and load conditions.

Fig. 8.Measured results of gate voltage and drain voltage of active switches. (a) S1 and S2 at 25% load with Vin=750 V. (b) S1 and S2 at 100% load with Vin=750 V. (c) S1 and S2 at 25% load with Vin=800 V. (d) S1 and S2 at 100% load with Vin=800 V.

Fig. 9.Measured results of gate voltage and drain voltage of active switches. (a) S3 and S4 at 25% load with Vin=750 V. (b) S3 and S4 at 100% load with Vin=750 V. (c) S3 and S4 at 25% load with Vin=800 V. (d) S3 and S4 at 100% load with Vin=800 V.

Fig. 10.Measured results of the resonant inductor currents iLr1-iLr3 at full load and (a) Vin=750 V. (b) Vin=800 V.

Fig. 11.Measured capacitor voltage waveforms of Cr1-Cr6 at Vin=750 V and full load. (a) vCr1-vCr6. (b) vCr1+vCr2, vCr3+vCr4 and vCr5+vCr6.

Fig. 12.Measured capacitor voltage waveforms of Cr1-Cr6 at Vin=800 V and full load. (a) vCr1-vCr6. (b) vCr1+vCr2, vCr3+vCr4 and vCr5+vCr6.

Fig. 13.Measured output diode currents at full load under (a) Vin=750 V (b) Vin=800 V.

Fig. 14.Measured efficiencies at different input voltages and load conditions.

 

V. CONCLUSION

A new soft switching DC/DC converter with balanced diode currents at the output side and low voltage stress of the power MOSFETs is presented for medium voltage applications. Three resonant circuits are adopted at the primary side and a series-connection of isolation transformers at the secondary side in order to balance the output diode currents of the proposed converter. The power rating of each resonant circuit is equal to half of the load power so that the current stresses of the passive components and transformer windings are reduced. Two half-bridge circuits with four spilt capacitors are adopted so that the voltage stress of the power MOSFETs are clamped at half of the input voltage. Two resonant capacitors Cr5 and Cr6 are also adopted to balance the input split capacitor voltages. When compared to conventional parallel three-level converters, the proposed converter has a lower power switch count. Finally, experiments with a 1.92 kW prototype are provided to demonstrate the performance of the converter.