DOI QR코드

DOI QR Code

Implementation of Integrated Receiver for Terrestrial/Cable/Satellite HD Broadcasting Services

유럽형 지상파/케이블/위성 멀티모드 HD 방송 수신이 가능한 통합 수신기 구현

  • Lee, Youn-Sung (School of Electrical and Electronic Engineering, Yonsei Univ.) ;
  • Kwon, Ki Won (Korea Electronics Technology Institute (KETI)) ;
  • Kim, Dong Ku (School of Electrical and Electronic Engineering, Yonsei Univ.)
  • Received : 2015.08.31
  • Accepted : 2015.11.09
  • Published : 2015.11.30

Abstract

This paper presents an integrated receiver to support multimode broadcasting standards such as DVB-T2, DVB-C2, and DVB-S2 in a single platform. The integrated receiver consists of a tuner block, a receiver engine, a frame processor, and an A/V decoder. The receiver engine includes a channel decoding engine and a demodulation engine to perform OFDM and APSK demodulations. The frame processor performs deinterleaving and BB frame decoding functions. The demodulator engine and the frame processor are implemented in two FPGA devices and DSP-based embedded software, respectively. To verify the functionality of the integrated receiver, it is tested in the laboratory. Commercial PC-based modulators are used to generate the DVB-T2, DVB-C2, and DVB-S2 modulated signals. The integrated receiver was tested under various operation modes as specified in the standards such as DVB-T2, DVB-C2, and DVB-S2 and showed successful operation in all the scenarios tested.

본 논문에서는 유럽형 2세대 디지털 지상파, 케이블, 위성 방송을 하나의 수신기로 수신할 수 있는 통합 수신기의 구현 방법을 제안한다. 통합 수신기는 튜너부, 수신기 엔진, 프레임 프로세서, A/V 복호기로 구성된다. 수신기 엔진은 DVB-T2, DVB-C2, DVB-S2에 대한 복조 및 채널 복호 기능을 수행하고, 프레임 프로세서는 디인터 리빙 및 프레임 디코딩 기능을 수행한다. 수신기 엔진은 2개의 FPGA로 구현되었고, 프레임 프로세서는 DSP 기반 임베디드 소프트웨어로 구현되었다. 구현된 통합 수신기를 검증하기 위해 실험실 환경에서 동작 실험을 진행하였고, DVB-T2, DVB-C2, DVB-S2 방송을 송신하기 위해 PC기반의 상용 송신기가 사용되었다. 실험 결과 다양한 동작 모드에서 수신 요구 사항을 모두 만족하였다.

Keywords

References

  1. ETSI EN 302 307 V1.2.1, Digital Video Broadcasting (DVB); Second generation framing structure, channel coding and modulation systems for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications (DVB-S2), Aug. 2009.
  2. ETSI EN 302 755 V1.3.1, Digital Video Broadcasting (DVB); Frame structure channel coding and modulation for a second generation digital terrestrial television broadcasting system (DVB-T2), Apr. 2012.
  3. ETSI EN 302 769 V1.2.1, Digital Video Broadcasting (DVB); Frame structure channel coding and modulation for a second generation digital transmission system for cable systems (DVB-C2), Apr. 2011.
  4. ETSI TS 102 831 V1.2.1, Digital Video Broadcasting (DVB); Implementation guidelines for a second generation digital terrestrial television broadcasting system (DVB-T2), Aug. 2012.
  5. ETSI TS 102 991 V1.2.1, Digital Video Broadcasting (DVB); Implementation guidelines for a second generation digital cable transmission system (DVB-C2), Jun. 2011.
  6. Silicon Labs, Si2167-C DVB-S2X /S2/T/C/S Digital Demodulator, Retrieved Oct. 20, 2015 from http://www.silabs.com/products/video/demodulator/Pages/Si2167.aspx.
  7. Sony, Sony Commercializes World's First Demodulator LSI for DVB-C2 Digital Cable TV Broadcast Standard, Retrieved Oct. 20, 2015 from http://www.sony.net/SonyInfo/News/Press/201109/11-110E/index.html.
  8. F. M. Gardner, "A BPSK /QPSK timing-error detector for sampled receivers," IEEE Trans. Commun., vol. 34, pp. 423-429, May 1986. https://doi.org/10.1109/TCOM.1986.1096561
  9. D. H. Kim and Y. H. Lee, "Incremental redundancy hybrid ARQ(IR-HARQ) scheme using block LDPC codes," J. KICS, vol. 38A, no. 8, pp. 662-668, Aug. 2013. https://doi.org/10.7840/kics.2013.38A.8.662
  10. J. W. Jung, H. C. Kwon, Y. J. Kim, S. H. Park, and S. R. Lee, "A study on high speed LDPC decoder algorithm based on DVB-S2 standard," J. KICS, vol. 38C, no. 3, pp. 311-317, Mar. 2013. https://doi.org/10.7840/kics.2013.38C.3.311
  11. I. K. Lee, M. H. Kim, D. G. Oh, and J. W. Jung, "A high speed LDPC decoder structure based on the HSS," J. KICS, vol. 38, no. 2, pp. 140-145, Feb. 2013.