한국전자통신학회논문지 (The Journal of the Korea institute of electronic communication sciences)

한국전자통신학회 (Korea Institute of Electronic Communication Science)
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0.13㎛ 기술의 shrink에 따른 DC Parameter 매칭에 관한 연구

A Study on the DC parameter matching according to the shrink of 0.13㎛ technology

  • 문성열 (전남대학교 전기및반도체공학과) ;
  • 강성준 (전남대학교 전기및반도체공학과) ;
  • 정양희 (전남대학교 전기및반도체공학과)
  • 투고 : 2014.09.01
  • 심사 : 2014.11.10
  • 발행 : 2014.11.30
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초록

본 논문은 기존의 poly length만의 축소와 달리 입, 출력 소자를 포함한 core 디바이스의 $0.13{\mu}m$ 디자인을 10% 축소하는 것으로 여러 채널 길이에 따른 body effect와 doping profile simulation을 해석하였다. 축소 전의 DC 파라미터 매칭을 위하여 게이트 산화막의 decoupled plasma nitridation 처리와 LDD(Lightly Doped Drain) 이온주입 전 TEOS(Tetraethylortho silicate) 산화막 $100{\AA}$ 그리고 LDD 이온주입을 22o tilt-angle(45o twist-angle)로 최적화하였고 그 결과 축소 전의 5%의 범위에서 매칭됨을 확인하였다.

This paper relates 10% shrink from $0.13{\mu}m$ design for core devices as well as input and output (I/O) devices different from previous poly length shrink size only. We analyzed body effect with different channel length and doping profile simulation. After fixing the gate oxide module process, LDD implant conditions were optimized such as decoupled plasma nitridation of gate oxide, TEOS oxide $100{\AA}$ before LDD implant and 22o tilt-angle(45o twist-angle) LDD implant respectively to match the spice DC parameters of pre-shrink and finally matched them within 5%.

키워드

참고문헌

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