JSTS:Journal of Semiconductor Technology and Science

  • 제14권5호
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  • Pages.673-681
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  • 2014
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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Low Specific On-resistance SOI LDMOS Device with P+P-top Layer in the Drift Region

  • Yao, Jia-Fei (College of Electronic Science and Engineering, Nanjing University of Posts and Telecommunications) ;
  • Guo, Yu-Feng (College of Electronic Science and Engineering, Nanjing University of Posts and Telecommunications) ;
  • Xu, Guang-Ming (College of Electronic Science and Engineering, Nanjing University of Posts and Telecommunications) ;
  • Hua, Ting-Ting (College of Electronic Science and Engineering, Nanjing University of Posts and Telecommunications) ;
  • Lin, Hong (College of Electronic Science and Engineering, Nanjing University of Posts and Telecommunications) ;
  • Xiao, Jian (College of Electronic Science and Engineering, Nanjing University of Posts and Telecommunications)
  • 투고 : 2014.06.22
  • 심사 : 2014.08.18
  • 발행 : 2014.10.30
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초록

In this paper, a novel low specific on-resistance SOI LDMOS Device with P+P-top layer in the drift region is proposed and investigated using a two dimensional device simulator, MEDICI. The structure is characterized by a heavily-doped $P^+$ region which is connected to the P-top layer in the drift region. The $P^+$ region can modulates the surface electric field profile, increases the drift doping concentration and reduces the sensitivity of the breakdown voltage on the geometry parameters. Compared to the conventional D-RESURF device, a 25.8% decrease in specific on-resistance and a 48.2% increase in figure of merit can be obtained in the novel device. Furthermore, the novel $P^+P$-top device also present cost efficiency due to the fact that the $P^+$ region can be fabricated together with the P-type body contact region without any additional mask.

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참고문헌

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