Journal of the Institute of Electronics and Information Engineers (전자공학회논문지)

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A Reconfigurable Multiplier Architecture Based on Memristor-CMOS Technology

멤리스터-CMOS 기반의 재구성 가능한 곱셈기 구조

  • Park, Byungsuk (College of Electrical and Computer Engineering, Chungbuk National University) ;
  • Lee, Sang-Jin (College of Electrical and Computer Engineering, Chungbuk National University) ;
  • Jang, Young-Jo (School of Electrical, Electronics & Communication Engineering, Korea University of Technology and Education) ;
  • Eshraghian, Kamran (College of Electrical and Computer Engineering, Chungbuk National University) ;
  • Cho, Kyoungrok (College of Electrical and Computer Engineering, Chungbuk National University)
  • Received : 2014.05.14
  • Accepted : 2014.10.06
  • Published : 2014.10.25
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Abstract

Multiplier performs a complex arithmetic operation in various signal processing algorithms such as multimedia and communication system. The multiplier also suffers from its relatively large signal propagation delay, high power dissipation, and large area requirement. This paper presents memristor-CMOS based reconfigurable multiplier reducing area occupation of the multiplier circuitry and increasing compatibility using optimized bit-width for various applications. The performance of the memristor-CMOS based reconfigurable multiplier are estimated with memristor SPICE model and 180 nm CMOS process under 1.8 V supply voltage. The circuit shows performance improvement of 61% for area, 38% for delay and 28% for power consumption respectively compared with the conventional reconfigurable multipliers. It also has an advantage for area reduction of 22% against a twin-precision multiplier.

곱셈기는 멀티미디어 통신 시스템과 같이 다양한 신호처리 알고리즘을 갖는 복잡한 연산을 수행한다. 곱셈기는 상대적으로 큰 전달 지연시간, 높은 전력 소모, 큰 면적을 갖는다. 이 논문은 멤리스터-CMOS 기반의 재구성 가능한 곱셈기를 제안하여 곱셈기 회로의 면적을 줄이고 다양한 응용프로그램에 최적화 된 비트폭을 제공한다. 멤리스터-CMOS 기반의 재구성 가능한 곱셈기의 성능은 1.8 V 공급전압에서 멤리스터 SPICE 모델과 180 nm CMOS 공정으로 검증했다. 검증 결과 제안한 멤리스터-CMOS 기반의 재구성 가능한 곱셈기는 종래의 것과 비교시 면적, 지연시간, 전력소모가 각각 61%, 38%, 28% 개선되었고, twin-precision 곱셈기와 면적 비교에서도 22% 개선되었다.

Keywords

References

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