전자공학회논문지 (Journal of the Institute of Electronics and Information Engineers)

  • 제51권9호
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  • Pages.67-74
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  • 2014
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  • 2287-5026(pISSN)
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  • 2288-159X(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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멤리스터-CMOS 기반의 잉여 이진 가산기 설계

Design of Redundant Binary Adder based on Memristor-CMOS

  • Ahn, Yeongyu (College of Electrical and Computer Engineering, Chungbuk National University) ;
  • Lee, Sang-Jin (College of Electrical and Computer Engineering, Chungbuk National University) ;
  • Kim, Seokman (College of Electrical and Computer Engineering, Chungbuk National University) ;
  • Eshraghian, Kamran (College of Electrical and Computer Engineering, Chungbuk National University) ;
  • Cho, Kyoungrok (College of Electrical and Computer Engineering, Chungbuk National University)
  • 투고 : 2014.03.24
  • 심사 : 2014.09.11
  • 발행 : 2014.09.25
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초록

본 논문은 멤리스터-CMOS 기반의 잉여 이진 부호화 자리수 (RBSD) 가산기를 제안한다. 기존의 RBSD 가산기는 리플 캐리 가산기에 비해 큰 면적을 차지한다. 또한 처리하는 비트 수가 적을 때 연산 속도가 느린 단점이 있다. 제안된 RBSD 가산기는 기존 RBSD 가산기의 단점을 보완하기 위해 멤리스터-CMOS 회로를 사용한다. 제안된 멤리스터-CMOS 기반의 RBSD 가산기는 기존 RBSD 가산기에 비해 단위 셀 면적이 45% 감소하였고, 지연시간이 24% 감소하였다. 제안된 멤리스터-CMOS 기반의 RBSD 가산기의 구현으로 인해 RBSD 가산기의 장점이 더욱 부각되고, 대용량 회로에서 더 큰 이득을 얻는다.

This paper presents a memristor-CMOS based RBSD adder. Conventional RBSD adders suffer bigger hardware due to the extra logic handling larger number of bits. The purpose of this paper is to improve the silicon surface area and the computation delay of conventional RBSD adders. The proposed method employs memristor-CMOS based circuit. The implementation results shows that the proposed memristor-CMOS based RBSD adder saves the cell area by 45%, and reduces time delay 24% compared to conventional RBSD adders. The proposed RBSD adder design can bring further area saving for large scale designs.

키워드

참고문헌

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