Investigation of InAs/InGaAs/InP Heterojunction Tunneling Field-Effect Transistors

Abstract

Tunneling field-effect transistors (TFETs) are very applicable to low standby-power application by their virtues of low off-current ($I_{off}$) and small subthreshold swing (S). However, low on-current ($I_{on}$) of silicon-based TFETs has been pointed out as a drawback. To improve $I_{on}$ of TFET, a gate-all-around (GAA) TFET based on III-V compound semiconductor with InAs/InGaAs/InP multiple-heterojunction structure is proposed and investigated. Its performances have been evaluated with the gallium (Ga) composition (x) for $In_{1-x}Ga_xAs$ in the channel region. According to the simulation results for $I_{on}$, $I_{off}$, S, and on/off current ratio ($I_{on}/I_{off}$), the device adopting $In_{0.53}Ga_{0.47}As$ channel showed the optimum direct-current (DC) performance, as a result of controlling the Ga fraction. By introducing an n-type InGaAs thin layer near the source end, improved DC characteristics and radio-frequency (RF) performances were obtained due to boosted band-to-band (BTB) tunneling efficiency.

1. Introduction

As the channel length (Lch) of conventional MOSFET scales down continuously, various problems such as shortchannel effects (SCEs) and high standby-power dissipation have been witnessed. Recently, tunneling field-effect transistor (TFET) based on band-to-band (BTB) tunneling mechanism has been researched as one of solutions for ultra-small MOSFETs aiming low standby-power applications. Owing to its merits including low off-current (Ioff) and small subthreshold swing (S), TFETs can be used in low-power and high-speed applications [1-4]. On the other hand, commercializing the silicon-based TFETs has not been successful due to their low on-current (Ion) characteristics. To enhance Ion, various kinds of compound semiconductors, structures, and gate insulator materials have been adopted to realize advanced TFETs. Especially as using source material of the high mobility and low energy band gap compared with Si, III-V compound semiconductors has been attracted such as InAs and InGaAs for TFETs [5-14].

In this paper, an InAs/InGaAs/InP multiple-heterojunction is applied to gate-all-around (GAA) TFETs. The gallium (Ga) composition (x) in the In1-xGaxAs-channel affects the total current, which makes it to be a control variable in optimizing the device performances. Other than searching for an optimum x, n-type doping in the InGaAs channel was introduced to study doping effects. Moreover, radio-frequency (RF) parameters were extracted from devices with different n-type channel lengths (Ln|InGaAs).

 

2. Device Characteristics

Fig. 1(a) shows a schematic of the proposed TFET with Lch = 30 nm, channel radius (Rch) = 10 nm, and gate oxide thickness (Tox) = 2 nm. The gate oxide was alumina (Al2O3). The doping concentrations of p+-source, p-- channel, and n+-drain regions were 1020, 1016, and 1018 cm-3, in sequence.

Devices were simulated with the trap-assisted tunneling (TAT) and nonlocal band-to-band (BTB) tunneling model showing higher accuracy compared to models with fixed constants provided in the device simulation package [15]. In fabrication, InGaAs and InAs can be epitaxially grown on InP substrate by molecular beam epitaxy (MBE) or metal-organic chemical vapor deposition (MOCVD) to make up the InAs/InGaAs/InP heterojunctions [16]. The lattice constant of InAs, In0.53Ga0.47As, and InP are 6.058 Å, 5.869Å, and 5.869Å, respectively, at room temperature [17]. In analyzing the simulation results, S was defined as the average slope between the onset point of drain current (ID) and the reference point at ID = 10-7 A/μm on the ID-VGS transfer curve. Ion was ID at VGS = VDS = 0.5 V (ID: drain current, VGS: gate-to-source voltage, VDS: drain-to-source voltage). The device in Fig. 1(b) is equipped with an additional n-type region near the source end to enhance the tunneling.

Fig. 1.Schematics of the GAA InAs/InGaAs/InP heterojunction TFETs (a) without and (b) with the n+ insertion layer near the source junction.

Fig. 2(a) shows the transfer curves of the proposed TFETs with different x values in In1-xGaxAs. Tunneling probability, T(E), induced from Wentzel-Kramers-Brillouin (WKB) approximation is expressed as follows:

Fig. 2.Transfer characteristics: (a) ID-VGS curves of GAA InAs/InGaAs/InP TFETs with different Ga fractions in the channel; (b) Energy-band diagrams along the channel with different Ga fractions at VGS = VDS = 0.5 V.

where is the reduced effective mass of considering and , electron and hole effective masses, Eg is energy bandgap, |e| is electron charge, ξ is the electric field, and ħ is the reduced Planck’s constant ( h / 2π ) [18,19]. As the Ga fraction gets lower, m* and Eg become smaller [20]. As shown in Eq. (1), T(E) increases in terms of smaller m* and Eg. For source InAs, m* = 0.0248 m0 and Eg = 0.35 eV as listed in the table of Fig. 2(b), by which greatly enhanced T(E) is expected [20,21]. Due to a relatively larger Eg of InP (1.34 eV), BTB tunneling between drain and channel in the off-state restrains ambipolar behavior mainly due to gate-induced drain leakage (GIDL). As shown in Fig. 2(b), even though Eg of channel InGaAs gets larger with higher Ga fraction, the source-to-channel effective tunneling barrier width does not change drastically. From the view points of Ioff and ambipolar behavior, higher x results in thicker channel-to-drain tunneling barrier, which effectively suppresses Ioff.

Fig. 3 shows the Ion, Ioff, S, and Ion/Ioff for the simulated devices as a function of x. As shown in Fig. 3(a), it is observed that both Ion and Ioff decrease as x increases. These parameters are in trade-off relation and higher Ion and lower Ioff cannot be obtained at the same time. Thus, it is necessary to put a weight on a narrowed number of parameters of interest in determining the Ga fraction. Fig. 3(b) shows S and Ion/Ioff as a function of x. Ion/Ioff at x = 0.47 (2.4×108) is 10 times higher than the value at x = 0.1. Also, S at x = 0.47 (32.4 mV/dec) is smaller compared with x = 0.1 case. x = 0.47 (In0.53Ga0.47As) can be a very good selection from S and Ion/Ioff viewpoint but it might be also changed to a lower value if Ion is regarded as the parameter of main interest (Fig. 3(a)).

Fig. 3.Direct-current (DC) characteristics: (a) Ion and Ioff; (b) S and Ion/Ioff as a function of x.

In reference to InAs homojunction GAA TFET indicated in a previous work [22], the purposed InAs/In0.53 Ga0.47As/InP TFET has been investigated for lower standby power application at drain voltage (VDS) of 0.2 V. Due to low VDS, the ambipolar behavior of InAs/In0.53Ga0.47As/InP TFET is more restrained as shown in Fig. 4. Although there are differences in the effective masses according to various channel diameters due to confinement, the electron effective mass of InAs in InAs/In0.53Ga0.47As/InP TFETs is close to the bulk value of 0.023m0 as d = 20 nm [22]. So, InAs/In0.53Ga0.47As/InP TFET has high current level.

Fig. 4.ID-VGS transfer curves of GAA InAs/In0.53Ga0.47As/ InP TFETs at VDS = 0.2 V.

 

3. n+-In0.53Ga0.47As Tunneling-boost Layer

Fig. 1(b) showed a schematic of GAA InAs/In0.53Ga0.47As/InP TFET with very thin n-type layer near the source junction. The locally introduced n-type region improves device performances. The n-type doping concentration was 5×1019 cm-3.

Fig. 5 (a) shows the ID-VGS curve of TFETs having n-type insertion layer with different lengths. Fig. 5 (b) shows S and Ion extracted from the transfer curves. In consideration of S and Ion, Ln|InGaAs of 3 nm can be considered to be an optimum value, where Ion/Ioff = 4.78×108, S=21 mV/dec, and Ion=1.33 mA/μm were obtained. The optimum values are more valued than those of GAA InAs/In0.53Ga0.47As/InP TFETs without n-type layer, where Ion/Ioff = 2.4×108, S = 32.4 mV/dec, and Ion = 368 μA/μm, respectively.

Fig. 5.(a) ID-VGS transfer curves of GAA InAs/In0.53Ga0.47As/InP with n-type insertion layer; (b) S and Ion with n-type insertion layer.

Fig. 6 shows RF performances in terms of cut-off frequency (fT), maximum oscillation frequency (fmax), and intrinsic delay time (τ) of InAs/In0.53Ga0.47As/InP TFETs with (filled circles) and without (open circles) the thin n-type insertion layer (thickness = 3 nm) to boost the tunneling efficiency. fT and fmax are expressed as follows [23]:

Fig. 6.RF performances of TFETs having In0.53Ga0.47As channel with and without the n-type thin layer in comparisons.

where gm, gds, Rg,eff, Rse, and Rg are the transconductance, source-drain conductance, external effective gate resistance, external source resistance, and gate resistance, in sequence. Cgd and Cgs are gate-drain and gate-source capacitances, respectively. From Eq. (2), fT is determined by input capacitance and gm. The n-type insertion layer has an effect on Cgs and gm. In case of a TFET, the inversion charges start to accumulate from drain to source direction with increasing VGS [24], which makes Cgd larger than Cgs. Since Cgd is dominant, the effect of Ln|InGaAs is insignificant on the sum of Cgd and Cgs. fT = 2.5 tera-hertz (THz) and fmax = 3 THz were obtained from the TFET with n-type tunneling-booster region, which are much higher than those from device without the thin layer. Although the current level of conventional TFETs must be deteriorated by tunneling barrier, the GAA InAs/In0.53Ga0.47As/InP TFET with n-type insertion layer demonstrates good RF performance due to its genuinely high current level. τ is defined by the following equation [25,26]:

From Eq. (4) and the simulation results, τ’s were 14.5 femto-seconds (fs) and 20.6 fs for the devices with and without the n-type insertion layer.

 

4. Conclusion

A GAA InAs/InGaAs/InP heterojunction TFET has been designed and optimized in terms of Ga fraction and its performances were investigated by simulation works. When x for channel In1-xGaxAs was selected to be 0.47 as an optimum value, Ion = 368 μA/μm, S = 32.4 mV/dec, and Ion/Ioff ratio = 2.41×108 were obtained. At the same Ga fraction, n-type thin layer with an optimum thickness of 3 nm was schemed for improvements in the RF performances as well as DC characteristics (Ion of 1.33 mA/μm and S of 21 mV/dec). Both fT and fmax in the THz-regime were traced from the optimized TFET device. It supports that optimally designed InAs/InGaAs/InP heterojunction TFET has a strong potential for high-performance DC and RF applications.