JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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A PVT-compensated 2.2 to 3.0 GHz Digitally Controlled Oscillator for All-Digital PLL

  • Kavala, Anil (Inter-University Semiconductor Research Center (ISRC) and the School of Electrical and Computer Engineering, Seoul National University) ;
  • Bae, Woorham (Inter-University Semiconductor Research Center (ISRC) and the School of Electrical and Computer Engineering, Seoul National University) ;
  • Kim, Sungwoo (Inter-University Semiconductor Research Center (ISRC) and the School of Electrical and Computer Engineering, Seoul National University) ;
  • Hong, Gi-Moon (Inter-University Semiconductor Research Center (ISRC) and the School of Electrical and Computer Engineering, Seoul National University) ;
  • Chi, Hankyu (Inter-University Semiconductor Research Center (ISRC) and the School of Electrical and Computer Engineering, Seoul National University) ;
  • Kim, Suhwan (Inter-University Semiconductor Research Center (ISRC) and the School of Electrical and Computer Engineering, Seoul National University) ;
  • Jeong, Deog-Kyoon (Inter-University Semiconductor Research Center (ISRC) and the School of Electrical and Computer Engineering, Seoul National University)
  • Received : 2014.05.13
  • Accepted : 2014.06.05
  • Published : 2014.08.30
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Abstract

We describe a digitally controlled oscillator (DCO) which compensates the frequency variations for process, voltage, and temperature (PVT) variations with an accuracy of ${\pm}2.6%$ at 2.5 GHz. The DCO includes an 8 phase current-controlled ring oscillator, a digitally controlled current source (DCCS), a process and temperature (PT)-counteracting voltage regulator, and a bias current generator. The DCO operates at a center frequency of 2.5 GHz with a wide tuning range of 2.2 GHz to 3.0 GHz. At 2.8 GHz, the DCO achieves a phase noise of -112 dBc/Hz at 10 MHz offset. When it is implemented in an all-digital phase-locked loop (ADPLL), the ADPLL exhibits an RMS jitter of 8.9 ps and a peak to peak jitter of 77.5 ps. The proposed DCO and ADPLL are fabricated in 65 nm CMOS technology with supply voltages of 2.5 V and 1.0 V, respectively.

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References

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