참고문헌
- G. Chien and P. R. Gray, "A 900-MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications," IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1996 -1999, Dec. 2000. https://doi.org/10.1109/4.890315
- H. H. Chang, J. U. Chang, C. Y. Kuo and S. I. Liu, "A 0.7-2GHz self-calibrated multiphase delaylocked loop," IEEE J. Solid-State Circuits, vol. 41, no. 5, pp. 1051-1061, May. 2006. https://doi.org/10.1109/JSSC.2006.874036
- J. M. Chou, Y. T. Hsieh and J. T Wu, "Phase averaging and interpolation using resistor strings or resistor rings for multi-phase clock generation," IEEE J. Trans. Circuits Syst. I. vol. 53, no. 5 pp. 984-991, May. 2006. https://doi.org/10.1109/TCSI.2006.869905
- K.-I Oh, L.-S Kim, K.-I Park, Y.-H Jun and K. Kim, "Low-jitter multi-phase digital DLL with closet edge selection scheme for DDR memory interface," Electron. Lett., vol. 44, no. 19, pp. 1385-1386, Sept. 2008. https://doi.org/10.1049/el:20081887
- K. J. Hsiao and T. C. Lee, "An 8-GHz to 10-GHz distributed DLL for multiphase clock generation," IEEE J. Solid-State Circuits, vol. 44, no. 9, pp. 1121-1122, Sept. 2009. https://doi.org/10.1109/JSSC.2009.2014023
- S. Hwang, K. Kim, J. Kim, S. Kim and C. Kim, "A self-calibrated DLL-based clock generator for an energy-aware EISC processor," IEEE Trans. VLSI Systems, vol. 21, no. 3, pp. 575-579, Mar. 2013. https://doi.org/10.1109/TVLSI.2012.2188656
- Young-Shig Choi, "A Negative Feedback Looped Voltage-Controlled Ring Oscillator with Frequency Voltage Converter," IEEE Trans. Microwave theory and techniques, vol. 61, no. 9, pp. 3271-3276, Sept. 2013. https://doi.org/10.1109/TMTT.2013.2276055