Journal of the Institute of Electronics and Information Engineers (전자공학회논문지)

The Institute of Electronics and Information Engineers (대한전자공학회)
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FinFET Gate Resistance Modeling and Optimization

FinFET 게이트 저항 압축 모델 개발 및 최적화

  • Lee, SoonCheol (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Kwon, Kee-Won (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Kim, SoYoung (College of Information and Communication Engineering, Sungkyunkwan University)
  • 이순철 (성균관대학교 정보통신대학) ;
  • 권기원 (성균관대학교 정보통신대학) ;
  • 김소영 (성균관대학교 정보통신대학)
  • Received : 2014.05.06
  • Accepted : 2014.07.30
  • Published : 2014.08.25
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Abstract

In this paper, the compact model for FinFET gate resistance is developed. Based on the FinFET geometry and material, the value of the gate resistance is extracted by Y-parameter analysis using 3D device simulator, Sentaurus. By dividing the gate resistance into horizontal and vertical components, the proposed gate resistance model captures the non-linear characteristics. The proposed compact model reflects the realistic gate structure which has two different materials (Tungsten, TiN) stacked. Using the proposed model, the number of fins for the minimum gate resistance can be proposed based on the variation of gate geometrical parameters. The proposed gate resistance model is implemented in BSIM-CMG. A ring-oscillator is designed, and its delay performance is compared with and without gate resistance.

본 논문에서는 실제 공정을 반영한 FinFET의 게이트 저항 압축모델을 개발하였다. 삼차원 소자 시뮬레이터 Sentaurus를 사용하여, Y-parameter 해석 방법을 적용하여 게이트 저항을 추출하여 제안하는 모델을 검증하였다. FinFET 게이트의 전기장이 수평 수직 방향으로 형성됨을 고려하여 모델링함으로써, FinFET 게이트 저항의 비선형성을 반영하였다. 현재 제작되고 있는 FinFET에서 게이트가 두 물질(Tungsten, TiN)로 적층된 구조일 수 있음을 고려하여, 비저항이 서로 다른 물질을 적층 시킨 구조에 대한 압축 모델을 개발하였다. 제안하는 모델을 사용하여, 게이트의 기하학적 구조 변수 변화에 따른 게이트 저항이 최소가 되는 fin의 수를 제안하였다. BSIM-CMG에 제안하는 모델을 구현한 후, ring-oscillator를 설계하고, 게이트 저항이 고려되지 않았을 때와 고려되었을 때의 각단의 신호지연을 회로 시뮬레이터를 통해 비교하였다.

Keywords

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