References
- G. Chien and P. R. Gray, "A 900-MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications," IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1996-1999, Dec. 2000. https://doi.org/10.1109/4.890315
- C. Kim, I. C. Hwang and S. M. Kang, "A low-power small-area 7.28 ps jitter 1 GHz DLL-based clock generator," IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1414-1420, Nov. 2002. https://doi.org/10.1109/JSSC.2002.803936
- K. J. Hsiao and T. C. Lee, "An 8-GHz to 10-GHz distributed DLL for multiphase clock generation," IEEE J. Solid-State Circuits, vol. 44, no. 9, pp. 2478-2487, Sept. 2009. https://doi.org/10.1109/JSSC.2009.2024804
- J. H. Nam and Young-Shig Choi, "A clock generator with jitter suppressed delay locked loop," IEEK SD, vol. 49, no. 7, pp. 17-22, July 2012.
- J. Choi, S. Kim, W. Kim K. Kim K. Lim, and J. Laskar, "A low power and wide range programmable clock generator with a high multiplication factor," IEEE Trans., VLSI Systems, vol. 19, no. 4, pp. 701-705, Apr. 2011. https://doi.org/10.1109/TVLSI.2009.2036433
- K. Ryu, D. Jung, and S. Jung, " A DLL with dual edge triggered phase detector for fast lock and low jitter clock generator" IEEE Trans. Circuits and Systems II, vol. 59, no. 9, pp. 1860-1870, Sept. 2012. https://doi.org/10.1109/TCSI.2011.2180453
- S. Hwang, K. Kim, J. Kim, S. Kim, and C. Kim, "A self-calibrated DLL-based clock generator for an energy-aware EISC processor," IEEE Trans., VLSI Systems, vol. 21, no. 3, pp. 575-579, Mar. 2013. https://doi.org/10.1109/TVLSI.2012.2188656
- Floyd M. Gardner, "Charge-Pump Phase-Lock Loop", IEEE J. Tran, on Communications, vol. COM-28, no, 11, pp. 1849-1858, Nov. 1980.
- Kyoohyun Lim, Chan-Hong Park, Dal-Soo Kim and Beomsup Kim, "A Low-Noise Phase-Locked Loop Design by Loop Bandwidth Optimization," IEEE J. Solid-State Circuits, vol. 35, no. 6, pp. 807-815, June. 2000. https://doi.org/10.1109/4.845184
- K. J. Wang, and I. Galton, "A discrete-time model for the design of type-II PLLs with passive sample loop filters," IEEE Trans. Circuits and Systems-I, vol. 58, no. 2, Feb. 2011.
- M. M. Elsayed, M. Abdul-Latif, E. Sanchez-Sinecio, "A spur-frequency-boosting PLL with a -74 dBc reference-spur suppression in 90 nm digital CMOS," IEEE J. Solid-State Circuits, vol. 48, no. 9, pp. 2104-2117, Sept. 2013. https://doi.org/10.1109/JSSC.2013.2266865
- Y-S Choi, J-D Oh, H-H Choi, "A phase-locked loop with a self-noise suppressing voltage controlled oscillator," IEEK-TC, vol. 47, no. 8. pp. 47-52, Aug. 2010.