References
- S. Karp and B. K. Gilbert, "Digital system design in the presence of single event upsets," IEEE Trans. Aerospace and Electronic Systems, vol. 29, no. 2, pp. 310-316, Apr. 1993. https://doi.org/10.1109/7.210069
- R. Harboe-Sorensen, E. Daly, F. Teston, H. Schweitzer, R. Nartallo, P. Perol, F. Vandenbussche, H. Dzitko, and J. Cretolle, "Observation and analysis of single event effects on-board the SOHO satellite," IEEE Trans. Nuclear Science, vol. 49, no. 3, pp. 1345-1350, Jun. 2002. https://doi.org/10.1109/TNS.2002.1039665
- D. Radaelli, H. Puchner, S. Wong, and S. Daniel, "Investigation of multi-bit upsets in a 150 nm technology SRAM device," IEEE Trans. Nucl. Sci., vol. 52, no. 6, pp. 2433-2437, Dec. 2005. https://doi.org/10.1109/TNS.2005.860675
- P. Reviriego, J. A. Maestro, and Sanghyeon Baeg, "Optimizing scrubbing sequences for advanced computer memories," IEEE Trans. Device and Materials Reliability, vol. 10, no. 2, pp. 192-200, Jun. 2010. https://doi.org/10.1109/TDMR.2009.2039481
- S. Satoh, Y. Tosaka, and S. A. Wender, "Geometric effect of multiple-bit soft errors induced by cosmic ray neutrons on DRAMs," IEEE Electron Device Letters., vol. 21, no. 6, pp. 310-312, Jun. 2000. https://doi.org/10.1109/55.843160
- E. Normand, "Single event upset at ground level," IEEE Trans. Nucl. Sci., vol. 43, no. 6, pp. 2742-2750, Dec. 1996. https://doi.org/10.1109/23.556861
- R. Morelos-Zaragoza, The Art of Error Correcting Coding, Wiley, 2002.
- S. Karp and B. K. Gilbert, "Digital system design in the presence of single event upsets," IEEE Trans. Aerospace and Electronic Systems, vol. 29, no. 2, pp. 310-316, Apr. 1993. https://doi.org/10.1109/7.210069
- A. M. Saleh, J. J. Serrano, and J. H. Patel, "Reliability of scrubbing recovery-techniques for RAMs," IEEE Trans. Reliability, vol. 39, no. 1, pp. 114-122, Apr. 1990. https://doi.org/10.1109/24.52622
- G. C. Yang, "Reliability of semiconductor RAMs with soft error scrubbing techniques," IEE Proc. in Computers and Digital Techniques, vol. 142, pp. 337-344, Sep. 1995.
- R. M. Goodman and M. Sayano, "The reliability of semiconductor RAM memories with on-chip error-correction coding," IEEE Trans. Information Theory, vol. 37, no. 3, pp. 884-896, May 1991. https://doi.org/10.1109/18.79957
- S. Baeg, S. Wen, and R. Wong, "SRAM interleaving distance selection with a soft error failure model," IEEE Trans. Nucl. Sci., vol. 56, pt. 2, no. 4, pp. 2111-2118, Aug. 2009. https://doi.org/10.1109/TNS.2009.2015312
- S.-M. Ryu, "Reliability analysis of interleaved memory against soft multiple bit errors," 2013 ICROS Conference, pp. 176-179, Dec. 2013.
- S.-M. Ryu and D.-J. Park, "Transient bit error recovery scheme for ROM-based embedded systems," IEEE Trans. Information and System, vol. EE88-D, no. 9, pp. 2209-2212, Sep. 2005.
- S. Baeg, S. Wen, and R. Wong, "Minimizing soft errors in TCAM devices: a probabilistic approach to determining scrubbing intervals," IEEE Trans. Circuits and Systems, vol. 57, no. 4, pp. 814-822, Apr. 2010. https://doi.org/10.1109/TCSI.2009.2025856
- Z. Ming, X. L. Yi, L. Chang, and Z. J. Wei, "Reliability of memories protected by multibit error correction codes against MBUs," IEEE Trans. Nuclear Science, vol. 58, no. 1, pp. 289- 295, Feb. 2011. https://doi.org/10.1109/TNS.2010.2099667