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DOI QR Code

Low-latency SAO Architecture and its SIMD Optimization for HEVC Decoder

  • Kim, Yong-Hwan (Smart Media Research Center, Korea Electronics Technology Institute) ;
  • Kim, Dong-Hyeok (Multimedia IP Research Center, Korea Electronics Technology Institute) ;
  • Yi, Joo-Young (Multimedia IP Research Center, Korea Electronics Technology Institute) ;
  • Kim, Je-Woo (Multimedia IP Research Center, Korea Electronics Technology Institute)
  • 투고 : 2013.10.20
  • 심사 : 2013.11.15
  • 발행 : 2014.02.28

초록

This paper proposes a low-latency Sample Adaptive Offset filter (SAO) architecture and its Single Instruction Multiple Data (SIMD) optimization scheme to achieve fast High Efficiency Video Coding (HEVC) decoding in a multi-core environment. According to the HEVC standard and its Test Model (HM), SAO operation is performed only at the picture level. Most realtime decoders, however, execute their sub-modules on a Coding Tree Unit (CTU) basis to reduce the latency and memory bandwidth. The proposed low-latency SAO architecture has the following advantages over picture-based SAO: 1) significantly less memory requirements, and 2) low-latency property enabling efficient pipelined multi-core decoding. In addition, SIMD optimization of SAO filtering can reduce the SAO filtering time significantly. The simulation results showed that the proposed low-latency SAO architecture with significantly less memory usage, produces a similar decoding time as a picture-based SAO in single-core decoding. Furthermore, the SIMD optimization scheme reduces the SAO filtering time by approximately 509% and increases the total decoding speed by approximately 7% compared to the existing look-up table approach of HM.

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참고문헌

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