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An Improved Quine-McCluskey Algorithm for Circuit Minimization

회로 최소화를 위한 개선된 Quine-McCluskey 알고리즘

  • Lee, Sang-Un (Dept. of Multimedia Eng., Gangneung-Wonju National University)
  • 이상운 (강릉원주대학교 멀티미디어공학과)
  • Received : 2013.12.24
  • Accepted : 2014.02.10
  • Published : 2014.03.31

Abstract

This paper revises the Quine-McCluskey Algorithm to circuit minimization problems. Quine-McCluskey method repeatedly finds the prime implicant and employs additional procedures such as trial-and-error, branch-and-bound, and Petrick's method as a means of circuit minimization. The proposed algorithm, on the contrary, produces an implicant chart beforehand to simplify the search for the prime implicant. In addition, it determines a set cover to streamline the search for $1^{st}$ and $2^{nd}$ essential prime implicants. When applied to 3-variable and 4-variable experimental data, the proposed algorithm has indeed proved to obtain the optimal solutions much more simply and accurately than the Quine-McCluskey method.

본 논문은 회로 최소화 문제에 대한 Quine-McCluskey 법을 개선한 알고리즘을 제안하였다. Quine-McCluskey 법은 주 내포 항을 반복적인 방법으로 찾고, 회로 최소화 방법으로 시행착오법, 분기한정법 또는 Petrick 법을 적용한다. 반면에 제안된 알고리즘은 사전에 항표를 생성하여 주 내포 항을 간단히 찾는 방법을 제안하였으며, 집합피복을 결정하는 방법을 적용하여 1차와 2차 필수 주 내포 항을 간단히 찾는 방법을 제안하였다. 3-변수와 4-변수 실험 데이터에 적용한 결과 제안된 알고리즘이 Quine-McCluskey 법에 비해 보다 간단하면서도 정확히 해를 구할 수 있었다.

Keywords

References

  1. V. Kabanets and J. Y. Cai, "Circuit Minimization Problem," Proceedings of 32nd Symposium on Theory of Computing, Portland, Oregon, USA, pp. 73-79, Jun. 2000.
  2. M. Karnaugh, "The Map Method for Synthesis of Combinational Logic Circuits," Transactions of the American Institute of Electrical Engineers, part I, Vol. 72, No. 9, pp. 593-599, Nov. 1953. https://doi.org/10.1109/TCE.1953.6371932
  3. N. Sarkar, K. Petrus, and H. Hossain, "Software Implementation of the Quine-McCluskey Algorithm for Logic Gate Minimisation," Proceedings of the NACCQ, pp. 375-378, Napier, New Zealand, Jul. 2001.
  4. R. K. Brayton, G. D. Hachtel, C. McMullen, and A. L. Sangiovanni-Vincentelli, "Logic Minimization Algorithms for VLSI Synthesis," Springer, 1984.
  5. N. V. Vinodchandran, "Nondeterministic Circuit Minimization Problem and Derandomizing Arthur-Merlin Games," International Journal of Foundations of Computer Science, Vol. 16, No. 6, Dec. 2005.
  6. R. Siggh, A. Arora, G. Singh, and J. Malhotra, "Circuit Minimization in VLSI Using PSO & GA Algorithms," International Journal of Engineering Trends and Technology, Vol. 3, No. 1, pp. 43-46, Feb. 2012.
  7. M. Morrison and N. Ranganathan, " A Novel Optimization Method for Reversible Logic Circuit Minimization," IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 182-187, Aug. 2013.
  8. S. R. Petrick, "A Direct Termination of the Irredundant Forms of a Boolean Function from the Set of Prime Implicants," Technical Report AFCRC-TR-56-110, Air Force Cambridge Res. Center, Cambridge, MA, USA, 1956.