Journal of information and communication convergence engineering

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
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Research Needs for TSV-Based 3D IC Architectural Floorplanning

  • Lim, Sung Kyu (School of Electrical and Computer Engineering, Georgia Institute of Technology)
  • Received : 2013.10.30
  • Accepted : 2014.01.13
  • Published : 2014.03.31
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Abstract

This article presents key research needs in three-dimensional integrated circuit (3D IC) architectural floorplanning. Architectural floorplaning is done at a very early stage of 3D IC design process, where the goal is to quickly evaluate architectural designs described in register-transfer level (RTL) in terms of power, performance, and reliability. This evaluation is then fed back to architects for further improvement and/or modifications needed to meet the target constraints. We discuss the details of the following research needs in this article: block-level modeling, through-silicon-via (TSV) insertion and management, and chip/package co-evaluation. The goal of block-level modeling is to obtain physical, power, performance, and reliability information of architectural blocks. We then assemble the blocks into multiple tiers while connecting them using TSVs that are placed in between hard IPs and inside soft IPs. Once a full-stack 3D floorplanning is obtained, we evaluate it so that the feedback is provided back to architects.

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References

  1. C. Liu, T. Song, J. Cho, J. Kim, J. Kim, and S. K. Lim, "Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC," in Proceedings of the 48th ACM/EDAC/IEEE Design Automation Conference, New York, NY, pp. 783-788, 2011.
  2. M. Jung, J. Mitra, D. Z. Pan, and S. K. Lim, "TSV stress-aware fullchip mechanical reliability analysis and optimization for 3D IC," in Proceedings of the 48th ACM/EDAC/IEEE Design Automation Conference, New York, NY, pp. 188-193, 2011.
  3. M. Jung, X. Liu, S. K. Sitaraman, D. Z. Pan, and S. K. Lim, "Fullchip through-silicon-via interfacial crack analysis and optimization for 3D IC," in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, pp. 563-570, 2011.
  4. J. S. Yang, K. Athikulwongse, Y. J. Lee, S. K. Lim, and D. Z. Pan, "TSV stress aware timing analysis with applications to 3D-IC layout optimization," in Proceedings of the 47th ACM/IEEE Design Automation Conference, Anaheim, CA, pp. 803-806, 2010.
  5. K. Athikulwongse, A. Chakraborty, J. S. Yang, D. Z. Pan, and S. K. Lim, "Stress-driven 3D-IC placement with TSV keep-out zone and regularity study," in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, pp. 669-674, 2010.
  6. T. Song and S. K. Lim, "A fine-grained co-simulation methodology for IR-drop noise in silicon interposer and TSV-based 3D IC," in Proceedings of the 20th IEEE Conference on Electrical Performance of Electronic Packaging and Systems, San Jose, CA, pp. 239-242, 2011.
  7. X. Zhao, M. Scheuermann, and S. K. Lim, "Analysis of DC current crowding in through-silicon-vias and its impact on power integrity in 3D ICs," in Proceedings of the 49th ACM/EDAC/IEEE Design Automation Conference, San Francisco, CA, pp. 157-162, 2012.

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