IEIE Transactions on Smart Processing and Computing

The Institute of Electronics and Information Engineers (대한전자공학회)
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A Low-Voltage Low-Power Opamp-Less 8-bit 1-MS/s Pipelined ADC in 90-nm CMOS Technology

  • Abbasizadeh, Hamed (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Rikan, Behnam Samadpoor (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Lee, Dong-Soo (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Hayder, Abbas Syed (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Lee, Kang-Yoon (College of Information and Communication Engineering, Sungkyunkwan University)
  • Received : 2014.02.20
  • Accepted : 2014.08.28
  • Published : 2014.12.31
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Abstract

This paper presents an 8-bit pipelined analog-to-digital converter. The supply voltage applied for comparators and other sub-blocks of the ADC were 0.7V and 0.5V, respectively. This low power ADC utilizes the capacitive charge pump technique combined with a source-follower and calibration to resolve the need for the opamp. The differential charge pump technique does not require any common mode feedback circuit. The entire structure of the ADC is based on fully dynamic circuits that enable the design of a very low power ADC. The ADC was designed to operate at 1MS/s in 90nm CMOS process, where simulated results using ADS2011 show the peak SNDR and SFDR of the ADC to be 47.8 dB (7.64 ENOB) and 59 dB respectively. The ADC consumes less than 1mW for all active dynamic and digital circuitries.

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References

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