References
- 양준원, 서용진, "고전압용 LDI 칩의 정전기 보호를 위한 ENNMOS 소자의 특성 개선", 통신위성우주산업연구회논문지, 제7권 제2호, pp.18-24, 2012.
- 양준원, 서용진, "CPS 이온주입을 통한 NEDSCR 소자의 정전 기 보호 성능 개선", 통신위성우주산업연구회논문지, 제8권 제 1호, pp.45-53, 2013.03
- 양준원, 김형호, 서용진, "DDIC 칩의 정전기 보호 소자로 적용 되는 GG_EDNMOS 소자의 고전류 특성 및 더블 스냅백 메커 니즘 분석", 통신위성우주산업연구회논문지, 제8권 제2호, pp.36-43, 2013.06.
- S. Dabral and T. J. Maloney, "Basic ESD and I/O Design", John Wiley, New York, 1998.
- M. P. J. Mergens, W. Wilkening, S. Mettler, H. Wolf, A. Stricker and W. Fichtner, "Analysis of lateral DMOS power devices under ESD stress conditions", IEEE Trans. Electron Devices, 47, pp. 2128-2137, 2000. https://doi.org/10.1109/16.877175
- B. C. Jeon, S. C. Lee, J. K. Oh, S. S. Kim, M. K. Han, Y.I. Jung, H. T. So, J. S. Shim and K. H. Kim, "ESD characterization of grounded-gate NMOS with 0.35um/18V technology employing transmission line pulser (TLP) test", in Proc. EOS/ESD Symp., pp. 362-372, 2002.
- G. Bosselli, S. Meeuwsen, T. Mouthaan and F. Kuper, "Investigations on double diffused MOS (DMOS) transistors under ESD zap conditions", in Proc. EOS/ESD Symp., pp. 11-18, 1999.
- A. Chatterjee and T. Polgreen, "A low-voltage triggering SCR for on-chip ESD protection at output and input pads," IEEE Electron Device Lett., vol.12, pp. 21-22, Jan. 1991. https://doi.org/10.1109/55.75685
- J. H. Lee, J. R. Shih, C. S. Tang, K. C. Liu, Y. H. Wu, R. Y. Shiue, T. C. Ong, Y. K. Peng, and J. T. Yue, "Novel ESD protection structure with embedded SCRLDMOS for smart power technology," in Proc. IEEE 40-th Annual Int. Reliab. Phys. Symp., pp. 156-161, 2002.
- M. D. Ker, H. H. Chang, and C. Y. Wu, "A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low voltage CMOS IC's," IEEE J. Solid-State Circuits, vol. 32, pp. 38-51, Jan. 1997. https://doi.org/10.1109/4.553176
- C. H. Lai, M. H. Liu, S. Su, T. C. Lu, and S. Pan, "A novel gate coupled SCR ESD protection structure with high latchup immunity for high-speed I/O pad," IEEE Electron Device Lett., vol. 25, pp. 328-330, May 2004. https://doi.org/10.1109/LED.2004.826529
- M. D. Ker, "Lateral SCR devices with low-voltage high-current triggering characteristics for output ESD protection in submicron CMOS technology," IEEE Trans. Electron Devices, vol. 45, pp. 849-860, Apr. 1998. https://doi.org/10.1109/16.662790
- M. P. J. Mergens, C. C. Russ, K. G.. Verhaege, J. Armer, P. C. Jozwiak, and R. Mohn, "High holding current SCRs (HHI-SCR) for ESD Protection and latch-up Immune IC operation,"in Proc. EOS/ESD Symp., pp. 14-21, 2002.
- M. Streibl, K. Esmark, A. Sieck, W. Stadler, M. Wendel, J. Szatkowski and H. Goner, "Harnessing the base-pushout effect for ESD protection in bipolar and BiCMOS technologies" in Proc. EOS/ESD Symp., pp. 73-82, 2002.