Journal of the Institute of Electronics and Information Engineers (전자공학회논문지)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Low Power Embedded Memory Design for Viterbi Decoder with Energy Optimized Write Operation

쓰기 동작의 에너지 감소를 통한 비터비 디코더 전용 저전력 임베디드 SRAM 설계

  • Tang, Hoyoung (School of Electrical Engineering, Korea University) ;
  • Shin, Dongyeob (School of Electrical Engineering, Korea University) ;
  • Song, Donghoo (School of Nano-Semiconductor, Korea University) ;
  • Park, Jongsun (School of Electrical Engineering, Korea University)
  • 당호영 (고려대학교 전기전자전파공학부) ;
  • 신동엽 (고려대학교 전기전자전파공학부) ;
  • 송동후 (고려대학교 나노반도체공학과) ;
  • 박종선 (고려대학교 전기전자전파공학부)
  • Received : 2013.07.22
  • Published : 2013.11.25
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Abstract

By exploiting the regular read and write access patterns of embedded SRAM memories inside Viterbi decoder, the memory architecture can be efficiently modified to reduce the power consumption of write operation. According to the experimental results with 65nm CMOS process, the proposed embedded memory used for Viterbi decoder achieves 30.84% of power savings with 8.92% of area overhead compared to the conventional embedded SRAM approaches.

비터비 디코더(Viterbi decoder)용 임베디드 SRAM은 범용(General purpose) CPU에 쓰이는 SRAM과 달리 읽기, 쓰기 동작이 비터비 복호 알고리즘에 따라 일정한 액세스 패턴을 갖고 동작한다. 이 연구를 통하여 제안된 임베디드 SRAM의 구조는 이러한 메모리 동작의 패턴에 최적화되어 워드라인과 비트라인에서 발생하는 불필요한 전력소모를 제거함으로써 쓰기 동작의 소모 전력을 크게 줄일 수 있다. 65nm CMOS 공정으로 설계된 비터비 디코더는 본 논문에서 제안된 SRAM 구조를 이용하여 기존의 임베디드 SRAM 대비 8.92%만큼 면적증가로 30.84% 소모 전력 감소를 이룩할 수 있었다.

Keywords

References

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