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RF Capacitive Coupling Link for 3-D ICs

3-D 집적회로용 RF 커패시티브 결합 링크

  • Choi, Chan-Ki (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Cui, Chenglin (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Kim, Seong-Kyun (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Kim, Byung-Sung (College of Information and Communication Engineering, Sungkyunkwan University)
  • 최찬기 (성균관대학교 정보통신대학) ;
  • ;
  • 김성균 (성균관대학교 정보통신대학) ;
  • 김병성 (성균관대학교 정보통신대학)
  • Received : 2013.07.17
  • Accepted : 2013.09.16
  • Published : 2013.10.31

Abstract

This paper presents a bandpass wireless 3-D chip to chip interface technique. The proposed technique uses direct amplitude modulation of the free running oscillator which especially utilizes the coupling capacitance between two stacked chips as a part of the resonator. Therefore, the oscillator is three dimensionally configured and a simple envelope detector can be used as a receiver without any additional matching circuitry. The proposed link was designed and fabricated using 110 nm CMOS technology and experimental results successfully showed the data transmission at a data rate of 2 Gb/s for the stacked chips with a thickness of 50 ${\mu}m$ consuming 4.32 mW. The sizes of the Tx and Rx chips are 0.045 $mm^2$ and 0.029 $mm^2$, respectively.

본 논문은 적층된 칩 사이의 3차원 대역 통과 무선 통신 인터페이스를 제안한다. 제안 방법은 적층된 칩 사이의 작은 커패시턴스를 포함한 3차원 공진기를 이용하여 자주 주파수 발진기(free running oscillator)를 구성하고, 이 발진기를 진폭 변조하여 추가적인 정합회로 없이 수신단에서 포락선 검파를 통해 신호를 검출한다. 제안 방법을 검증하기 위해 110 nm CMOS 공정을 사용하여 송수신 칩을 설계하고, 제작하여 50 ${\mu}m$ 두께의 칩 사이에 2 Gb/s의 데이터 전송 속도를 확인하였다. 제작한 칩은 동작전압 1.2 V를 사용하며, 송수신 칩을 합하여 4.32 mW의 전력을 소모한다. 칩의 크기는 송신단은 0.045 $mm^2$이고, 수신단은 0.029 $mm^2$이다.

Keywords

References

  1. W. R. Davis, J. Wilson, S. Mick, and J. Xu, "Demystifing 3D ICs: The pros and cons of vertical", IEEE Design & Test of Computers, vol. 22, no. 6, pp. 498-510, Nov.-Dec. 2005. https://doi.org/10.1109/MDT.2005.136
  2. 김소영, "3D IC에서의 인터페이스 기술", 대한전자공학회지, 36(9), pp. 1001-1009, 2009년 9월.
  3. N. Miura, T. Kuroda, "Inductive - coupling transceiver for 3D system integration", IEEE Integrated Circuit Design and Technology(ICICDT), pp. 1-4, 2007.
  4. H. Ishikuro, N. Miura, and T. Kuroda, "Wideband inductive-coupling interface for high-performance portable system", IEEE Custom Integrated Circuits Conference(CICC), pp. 13-20, 2007.
  5. M. Saen, K. Osada, and Kuroda, "3-D system integration of processor and multi-stacked SRAMs using inductive-coupling link", IEEE J. Solid-State Circuits, vol. 45, no. 4, pp 856-862, Apr. 2010. https://doi.org/10.1109/JSSC.2010.2040310
  6. K. Ikeuchi, M. Takamiya, and T. Sakurai, "Through silicon capacitive coupling(TSCC) interface for 3D stacked dies", IEEE 3D Systems Integration Conference, pp. 1-5, 2012.
  7. M. Scandiuzzo, R. Cardu, S. Cani, S. Spolzino, L. Perugini, E. Franchi, R. Canegallo, and R. Guerrieri, "3 D system on chip memory interface based on modeled capacitive coupling interconnections", IEEE 3 D Systems Integration Conference, pp. 1-4, 2010.
  8. Gu Qun, Z. Xu, Jenwei Ko, and, M. -C. F. Chang, "Two 10 Gb/s/pin low-power interconnect methods for 3D ICs", IEEE International Solid State Circuits Conference(ISSCC), pp. 448-614, 2007.