JSTS:Journal of Semiconductor Technology and Science

  • 제13권5호
  • /
  • Pages.459-464
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  • 2013
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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A Reset-Free Anti-Harmonic Programmable MDLL-Based Frequency Multiplier

  • Park, Geontae (Electronic and Electrical Engineering, Hongik University) ;
  • Kim, Hyungtak (Electronic and Electrical Engineering, Hongik University) ;
  • Kim, Jongsun (Electronic and Electrical Engineering, Hongik University)
  • 투고 : 2013.01.21
  • 심사 : 2013.05.20
  • 발행 : 2013.10.31
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초록

A reset-free anti-harmonic programmable multiplying delay-locked loop (MDLL) that provides flexible integer clock multiplication for high performance clocking applications is presented. The proposed MDLL removes harmonic locking problems by utilizing a simple harmonic lock detector and control logic, which allows this MDLL to change the input clock frequency and multiplication factor during operation without the use of start-up circuitry and external reset. A programmable voltage controlled delay line (VCDL) is utilized to achieve a wide operating frequency range from 80 MHz to 1.2 GHz with a multiplication factor of 4, 5, 8, 10, 16 and 20. This MDLL achieves a measured peak-to-peak jitter of 20 ps at 1.2 GHz.

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참고문헌

  1. S. Tam. S. Rusu, U. N. Desai, R. Kim, J. Zhang, and I. Young, "Clock generation and distribution for the first IA-64 microprocessor," IEEE J. Solid- State Circuits, Vol. 35, pp. 1545-1552, Nov., 2000. https://doi.org/10.1109/4.881198
  2. G. Chien and P. Gray, "A 900-MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications," IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 202-203, Feb., 2000.
  3. Ramin Farjad-Rad, William Dally, Hiok-Tiaq Ng, Ramesh Senthinathan, M.-J. Edward Lee, "A lowpower multiplying DLL for low jitter multigigahertz clock generation in highly integrated digital chips," IEEE J. Solid-State Circuits, vol. 37, pp. 1804-1812, Dec., 2002. https://doi.org/10.1109/JSSC.2002.804340
  4. R. Farjad-Rad, A. Nguyen, J. M. Tran, J. Poulton, W. Dally, J. Edmondson, R. Senthinathan, R. Rathi, M. Lee, and N. Hiok-Tiaq, "A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os", IEEE J. Solid-State Circuits, vol. 39, pp. 1553-1561, Sep., 2004. https://doi.org/10.1109/JSSC.2004.831457
  5. Qingjin Du, Jingcheng Zhuang, and Tad Kwasniewski, "A low-phase noise, anti-harmonic programmable DLL frequency multiplier with period error compensation for spur reduction," IEEE TRANS. ON CIRCUITS AND SYSTEMS II, vol. 53, no. 11, pp. 1205-1209, Nov., 2006. https://doi.org/10.1109/TCSII.2006.883103
  6. Chuan-Kang Liang, Rong-Jyi Yang, and Shen-Iuan Liu, "An All-Digital Fast-Locking Programmable DLL-Based Clock Generator," IEEE TRANS.ON CIRCUITS AND SYSTEMS I, vol. 55, no. 1, pp. 361-369, Feb., 2008. https://doi.org/10.1109/TCSI.2007.913612

피인용 문헌

  1. An Area-Efficient Multi-Phase Fractional-Ratio Clock Frequency Multiplier vol.16, pp.1, 2016, https://doi.org/10.5573/JSTS.2016.16.1.143
  2. A 2–4 GHz fast-locking frequency multiplying delay-locked loop vol.14, pp.2, 2017, https://doi.org/10.1587/elex.13.20161056
  3. A Fast-Locking All-Digital Multiplying DLL for Fractional-Ratio Dynamic Frequency Scaling vol.65, pp.3, 2018, https://doi.org/10.1109/TCSII.2017.2688369