JSTS:Journal of Semiconductor Technology and Science

  • 제13권5호
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  • Pages.465-472
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  • 2013
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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Low-Complexity Triple-Error-Correcting Parallel BCH Decoder

  • Yeon, Jaewoong (Dept. of Information and Communication Engr., Inha University) ;
  • Yang, Seung-Jun (Dept. of Information and Communication Engr., Inha University) ;
  • Kim, Cheolho (Dept. of Information and Communication Engr., Inha University) ;
  • Lee, Hanho (Dept. of Information and Communication Engr., Inha University)
  • 투고 : 2013.04.21
  • 심사 : 2013.07.18
  • 발행 : 2013.10.31
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초록

This paper presents a low-complexity triple-error-correcting parallel Bose-Chaudhuri-Hocquenghem (BCH) decoder architecture and its efficient design techniques. A novel modified step-by-step (m-SBS) decoding algorithm, which significantly reduces computational complexity, is proposed for the parallel BCH decoder. In addition, a determinant calculator and a error locator are proposed to reduce hardware complexity. Specifically, a sharing syndrome factor calculator and a self-error detection scheme are proposed. The multi-channel multi-parallel BCH decoder using the proposed m-SBS algorithm and design techniques have considerably less hardware complexity and latency than those using a conventional algorithms. For a 16-channel 4-parallel (1020, 990) BCH decoder over GF($2^{12}$), the proposed design can lead to a reduction in complexity of at least 23 % compared to conventional architecttures.

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참고문헌

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피인용 문헌

  1. Low-Complexity Non-Iterative Soft-Decision BCH Decoder Architecture for WBAN Applications vol.16, pp.4, 2016, https://doi.org/10.5573/JSTS.2016.16.4.488
  2. Fast Decoding ECC for Future Memories vol.34, pp.9, 2016, https://doi.org/10.1109/JSAC.2016.2603698