JSTS:Journal of Semiconductor Technology and Science

  • 제13권4호
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  • Pages.367-380
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  • 2013
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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DOI QR코드

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An Analytical Model for the Threshold Voltage of Short-Channel Double-Material-Gate (DMG) MOSFETs with a Strained-Silicon (s-Si) Channel on Silicon-Germanium (SiGe) Substrates

  • Bhushan, Shiv (Department of Electronics and Communication Engineering, Nation al Institute of Technology) ;
  • Sarangi, Santunu (Department of Electronics and Communication Engineering, Nation al Institute of Technology) ;
  • Gopi, Krishna Saramekala (Department of Electronics and Communication Engineering, Nation al Institute of Technology) ;
  • Santra, Abirmoya (Department of Electronics and Communication Engineering, Nation al Institute of Technology) ;
  • Dubey, Sarvesh (Department of Electronics Engineering, IIT(BHU)) ;
  • Tiwari, Pramod Kumar (Department of Electronics and Communication Engineering, Nation al Institute of Technology)
  • 투고 : 2013.02.10
  • 심사 : 2013.04.09
  • 발행 : 2013.08.31
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초록

In this paper, an analytical threshold voltage model is developed for a short-channel double-material-gate (DMG) strained-silicon (s-Si) on silicon-germanium ($Si_{1-X}Ge_X$) MOSFET structure. The proposed threshold voltage model is based on the so called virtual-cathode potential formulation. The virtual-cathode potential is taken as minimum channel potential along the transverse direction of the channel and is derived from two-dimensional (2D) potential distribution of channel region. The 2D channel potential is formulated by solving the 2D Poisson's equation with suitable boundary conditions in both the strained-Si layer and relaxed $Si_{1-X}Ge_X$ layer. The effects of a number of device parameters like the Ge mole fraction, Si film thickness and gate-length ratio have been considered on threshold voltage. Further, the drain induced barrier lowering (DIBL) has also been analyzed for gate-length ratio and amount of strain variations. The validity of the present 2D analytical model is verified with ATLAS$^{TM}$, a 2D device simulator from Silvaco Inc.

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