JSTS:Journal of Semiconductor Technology and Science

  • 제13권2호
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  • Pages.87-97
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  • 2013
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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Impact Analysis of NBTI/PBTI on SRAM VMIN and Design Techniques for Improved SRAM VMIN

  • 투고 : 2012.04.25
  • 심사 : 2012.09.04
  • 발행 : 2013.04.30
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초록

Negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) are critical circuit reliability issues in highly scaled CMOS technologies. In this paper, we analyze the impacts of NBTI and PBTI on SRAM $V_{MIN}$, and present a design solution for mitigating the impact of NBTI and PBTI on SRAM $V_{MIN}$. Two different types of SRAM $V_{MIN}$ (SNM-limited $V_{MIN}$ and time-limited $V_{MIN}$) are explained. Simulation results show that SNM-limited $V_{MIN}$ is more sensitive to NBTI while time-limited $V_{MIN}$ is more prone to suffer from PBTI effect. The proposed NBTI/PBTI-aware control of wordline pulse width and woldline voltage improves cell stability, and mitigates the $V_{MIN}$ degradation induced by NBTI/PBTI.

키워드

참고문헌

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피인용 문헌

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  2. Comprehensive Circuit Failure Prediction for Logic and SRAM Using Virtual Aging vol.35, pp.6, 2015, https://doi.org/10.1109/MM.2015.136
  3. STABLE: Stress-Aware Boolean Matching to Mitigate BTI-Induced SNM Reduction in SRAM-Based FPGAs vol.67, pp.1, 2018, https://doi.org/10.1109/TC.2017.2725952