References
- International Technology Roadmap for Semiconductor. [Online]. Available: http://www.itrs.net/reports. html.
- R. Senthinathan, J. L. Prince, "Simultaneous switching ground noise calculation for packaged CMOS devices," IEEE J. Solid-State Circuits, vol. 26, no. 11, pp. 1724-1728, Nov. 1991. https://doi.org/10.1109/4.98995
- K. Slattery, J. P. Muccioli, and T. North, "Characterization of the RF emissions from a family of microprocessors using a 1 GHz TEM cell," in Proc. IEEE EMC Symp., Austin, TX, pp. 203-207, 1997.
- B. Vrignon, S. Bendhia, E. Lamoureux, and E. Sicard, "Characterization and modeling of parasitic emission in deep submicron CMOS," IEEE Trans. Electromagn. Compat., vol. 47, no. 2, pp. 382-385, May 2005. https://doi.org/10.1109/TEMC.2005.847408
- J. Kim, H. Kim, W. Ryu, and J. Kim, "Effects of onchip and off-chip decoupling capacitors on electromagnetic radiation emission," in Proc. Electron. Compon. Technol. Conf., pp. 610-614, 1998.
- M. P. Robinson, T. M. Benson, C. Christopoulos, J. F. Dawson, M. D. Ganley, A. C. Marvin, S. J. Porter, D. W. P. Thomas, and J. D. Turner, "Effect of logic family on radiated emissions from digital circuits," IEEE Trans. Electromagn. Compat., vol. 40, no. 3, pp. 288-293, Aug. 1998. https://doi.org/10.1109/15.709429
- I. Chahine, M. Kadi, E. Gaboriaud, A. Louis, and B. Mazari, "Characterization and modeling of the susceptibility of integrated circuits to conducted electromagnetic disturbances up to 1 GHz," IEEE Trans. Electromagn. Compat., vol. 50, no. 2, pp. 285-293, May 2008. https://doi.org/10.1109/TEMC.2008.918983
- A. Boyer, B. Li, S. Ben Dhia, B. Vrignon, and C. Lemoine, "Development of an immunity model of a phase-locked loop," in Proc. Asia-Pacific Symp. Electromagn. Compat., May 2011.
- B. Pu, J. J. Lee, S. S. Kwak, S. Y. Kim, and W. Nah, "Electromagnetic susceptibility analysis of ICs using DPI method with consideration of PDN," in Proc. Asia-Pacific Symp. Electromagn. Compat., Singapore, pp. 77-80, 2012.
- A. Alaeldine, R. Perdriau, M. Ramdani, J. L. Levant, and M. Drissi, "A direct power injection model for immunity prediction in integrated circuits," IEEE Trans. Electromagn. Compat., vol. 50, no. 1, pp. 52-62, Feb. 2008. https://doi.org/10.1109/TEMC.2007.911920
- J. S. Pak, J. Kim, J. Cho, K. Kim, T. Song, S. Ahn, J. Lee, H. Lee, K. Park, and J. Kim, "PDN impedance modeling and analysis of 3D TSV IC by using proposed P/G TSV array model based on separated P/G TSV and Chip-PDN models," IEEE Trans. Compon. Packag. Tech., vol. 1, no. 2, pp. 208-219, Feb. 2011. https://doi.org/10.1109/TCPMT.2010.2101771
- B. Pu, J. S. Lee, and W. Nah, "Electrical parameter extraction of high performance package using PEEC method," JKIEES, vol. 11, no. 1, pp. 62-69, Mar. 2011.
- Integrated Circuits, Measurement of Electromagnetic Immunity, 150 kHz-1 GHz,-Part 4: Direct RF Power Injection Method, International Electrotechnical Commission Standard IEC 62132-4, 2006.
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