DOI QR코드

DOI QR Code

반도체 웨이퍼 고속 검사를 위한 GPU 기반 병렬처리 알고리즘

The GPU-based Parallel Processing Algorithm for Fast Inspection of Semiconductor Wafers

  • 박영대 (호서대학교 전자공학과) ;
  • 김준식 (호서대학교 전자공학과) ;
  • 주효남 (호서대학교 디지털디스플레이공학과)
  • Park, Youngdae (Dept. of Electronics Engineering, Hoseo University) ;
  • Kim, Joon Seek (Dept. of Electronics Engineering, Hoseo University) ;
  • Joo, Hyonam (Dept. of Digital Display Engineering, Hoseo University)
  • 투고 : 2013.08.20
  • 심사 : 2013.10.04
  • 발행 : 2013.12.01

초록

In a the present day, many vision inspection techniques are used in productive industrial areas. In particular, in the semiconductor industry the vision inspection system for wafers is a very important system. Also, inspection techniques for semiconductor wafer production are required to ensure high precision and fast inspection. In order to achieve these objectives, parallel processing of the inspection algorithm is essentially needed. In this paper, we propose the GPU (Graphical Processing Unit)-based parallel processing algorithm for the fast inspection of semiconductor wafers. The proposed algorithm is implemented on GPU boards made by NVIDIA Company. The defect detection performance of the proposed algorithm implemented on the GPU is the same as if by a single CPU, but the execution time of the proposed method is about 210 times faster than the one with a single CPU.

키워드

참고문헌

  1. J. S. Lee, "Automatic classification algorithm of defects in semiconductor package molding surface inspection using pattern recognition," M. S. Thesis (in Korean), Hoseo University, 2009.
  2. R. Bertz and P. Leahy, "Inspection Challenges of Leadless Packages," Proc. SEMOCPN, pp. 418-422, 2002.
  3. S. J. Nam and K. S. Hahn, "Implementation of automated defect detection and classification system for semiconductor wafers," Proc. of the 28th KISS Fall Comference (in Korean), vol. 28, no. 2, pp. 334-336, 2001.
  4. K. S. Jang and C. H. Jeon "Classification rule-based defect pattern detection of semiconductor wafer map," Proc. of 2005 KIIE Fall Conference (in Korean), pp. 131-139, 2005.
  5. S. Che, M. Boyer, J. Meng, D. Tarjan, J. W. Sheaffer, and K. Skadron, "A performance study of general- purpose applications on graphics processors using CUDA," Journal of Parallel and Distributed Computing, vol. 68, no. 10, pp. 1370-1380, 2008. https://doi.org/10.1016/j.jpdc.2008.05.014
  6. Y. G. Yeom and Y. K. Cho, "High-speed implementation of block ciphers on graphics processing units using CUDA library," Journal of the Korea Institute of Information Security and Cryptology (in Korean), vol. 18, no. 3, pp. 23-31, 2008.
  7. M. Moazeni, A. Bui, and M. Sarrafzadeh, "A memory optimization technique for software-managed scratchpad memory if GPUs," 2009 IEEE 7th Symposium on Application Specific Porcessors, pp. 43-49, 2009.
  8. NVIDIA, C. U. D. A. NVIDIA CUDA Programming Guide. 2011.
  9. T. J. Park, J. M. Woo, and C. H. Kim, "CUDA-based parallel bi-conjugate gradient matrix solver for BioFET simulation," Journal of the Institute of Electronics Engineers of Korea (in Korean), vol. 48, no. 1, pp. 90-100, 2011.
  10. G. Vialaneix and T. Boubekeur, "SBL mesh filter: fast separable approximation of bilateral mesh filtering," ACM SIGGRAPH 2011 Talks. ACM, p. 24, 2011.
  11. V. Areekul, U. Watchareeruetai, and S. Tantaratana, "Fast separable gabor filter for fingerprint enhancement," Biometric Authentication. Springer Berlin Heidelberg, pp. 403-409, 2004.
  12. S. Kurra, N. K. Singh, and P. R. Panda, "The impact of loop unrolling on controller delay in high level synthesis," In IEEE Design, Automation & Test in Europe Conference & Exhibition, pp. 1-6, 2007.