Journal of Welding and Joining

The Korean Welding and Joining Society (대한용접접합학회)
권호 표지
DOI QR코드

DOI QR Code

Fracture Mode Analysis with ISB Bonding Process Parameter for 3D Packaging

3차원 적층 패키지를 위한 ISB 본딩 공정의 파라미터에 따른 파괴모드 분석에 관한 연구

  • 이영강 (과학기술연합대학원대학교 나노메카트로닉스학과) ;
  • 이재학 (한국기계연구원 초정밀시스템연구실) ;
  • 송준엽 (한국기계연구원 초정밀시스템연구실) ;
  • 김형준 (한국기계연구원 초정밀시스템연구실)
  • Received : 2013.11.06
  • Accepted : 2013.11.25
  • Published : 2013.12.31
Download PDF
⟨ Previous Next ⟩

Abstract

3D packaging technology using TSV (Through Silicon Via)has been studied in the recent years to achieve higher performance, lower power consumption and smaller package size because electrical line is shorter electrical resistivity than any other packaging technology. To stack TSV chips vertically, reliable and robust bonding technology is required because mechanical stress and thermal stress cause fracture during the bonding process. Cu pillar/solder ${\mu}$-bump bonding process is usually to interconnect TSV chips vertically although it has weak shape to mechanical stress and thermal stress. In this study, we suggest Insert-Bump (ISB) bonding process newly to stack TSV chips. Through experiments, we tried to find optimal bonding conditions such as bonding temperature and bonding pressure. After ISB bonding, we observed microstructure of bump joint by SEM and then evaluated properties of bump joint by die shear test.

Keywords

References

  1. Amkor Technology : 3D & Stacked Die Packaging, Technology Solution, TS 104D, 2009
  2. P.Garrou, C.Bower and P.Ramm : Handbook of 3D Integration: Technology and Applications of 3D Integrated Circuits, WILEY-VCH, 2008
  3. J.M. Yannou : 3D TSV interconnects: Equipment & materials, Yole Development, 2008
  4. S.F. Al-sarawi, D. Abbott and P.D. Franzon : A review of 3-D packaging technology, IEEE Transactions, 21-1 (1998), 2-14
  5. J.Y. Song, J.H. Lee, T.H. Ha, C.W. Lee and C.D. Yoo : 3D Packaging Process using TSV and Bonding Machine Technology, Journal of the Korean Society for Precision Engineering, 26-12 (2009), 9-17 (in Korean)
  6. Korea Institute of Machinery & Materials : 반도체 칩 적층 패키지 및 그 제조 방법, KR, 10-1144082 (2012) (in Korean)
  7. Y.H. Kim and S.R. Lee : A study of Intermetetallic Compound Growth in the Sn/Cu and Sn/Ni Couples (I): Intermetallic Compound Formation and Growth Kinetics, Journal of the Korean Institute of Surface Engineering, 22-1 (1989), 3-9 (in Korean)
  8. J.H. Yang, H.Y. Cho, Y.H. Kim : Reflow of Sn Solder Bumps using Rapid Thermal Annealing method and Intermetallic Formation, Journal of the Microelectronics & Packaging Society, 15-4 (2008), 1-7 (in Korean)
  9. C.B. Lee, S.B. Jung, Y.E. Shin and C.C. Shur : Effect of Isothermal Aging on Ball Shear Strength in BGA Joints with Sn-3.5Ag-0.75Cu Solder, Materials Transactions, 43-8 (2002), 1858-1863 https://doi.org/10.2320/matertrans.43.1858
  10. J.H.L. Pang, D.Y.R. Chong and T.H. Low : Thermal cycling analysis of flip-chip solder joint reliability, IEEE transactions, 24-4 (2001), 705-712
  11. H.W. Tseng, C.T. Lu, Y.H. Hsiao, P.L. Liao, Y.C.Chuang and C.Y. Liu : Electromigration-induced failures at Cu/Sn/Cu flip-chip joint interfaces, Microelectronics Reliability, 50-8 (2010), 1159-1162 https://doi.org/10.1016/j.microrel.2010.05.002
  12. I.R. Shon, J.W. Choi and T. Narita : Fracture Behavior of Oxide Scales and Influence of Oxide Scales on the Strength of Materials, Transactions of Materials Processing, 13-1 (2004), 72-77 (in Korean) https://doi.org/10.5228/KSPP.2004.13.1.072
  13. 恩澤忠男 and Y.S. Kim : 확산접합의 원리와 기초, Journal of KWS, 6-1 (1988), 2-10 (in Korean)
  14. Y.K. Lee, Y.H. Ko, S.H. Yoo and C.W. Lee : Interfacial Miicrostructure and Mechanical Property of Au Stud Bump Joined by Flip Chip Bonding with Sn-3.5Ag Solder, Journal of KWJS, 29-6 (2011), 685-690 (in Korean)
  15. S.C. Hong, W.G. Lee, J.K. Park, W.J. Kim and J.P. Jung : Cu Filling into TSV and non-PR Sn bumping for 3 Dimension Chip Packaging, Journal of KWJS, 29-1 (2011), 9-13 (in Korean)