전자공학회논문지 (Journal of the Institute of Electronics and Information Engineers)

대한전자공학회 (The Institute of Electronics and Information Engineers)
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이퀄라이저 적응기를 포함한 12.5-Gb/s 저전력 수신단 설계

A 12.5-Gb/s Low Power Receiver with Equalizer Adaptation

  • 강정명 (성균관대학교 정보통신대학) ;
  • 정우철 (성균관대학교 정보통신대학) ;
  • 권기원 (성균관대학교 정보통신대학) ;
  • 전정훈 (성균관대학교 정보통신대학)
  • Kang, Jung-Myung (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Jung, Woo-Chul (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Kwon, Kee-Won (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Chun, Jung-Hoon (College of Information and Communication Engineering, Sungkyunkwan University)
  • 투고 : 2013.10.10
  • 심사 : 2013.11.25
  • 발행 : 2013.12.25
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초록

본 논문에서는 이퀄라이저 적응기(adaptation)를 포함하는 12.5 Gb/s 저전력 수신단 설계에 대해서 기술한다. 샘플러와 직렬 변환기를 사용한 저전력 아날로그 이퀄라이저 적응기를 구현함으로써 채널과 칩 공정 변화에 능동적으로 적응할 수 있으며 그 적응 원리에 대해서 설명한다. 또한 저전력을 위한 전압 모드 송신기의 접지 기반 차동 신호를 수신하는 기술에 대해서 설명하였다. 17.6 dB의 피킹 이득을 갖는 CTLE(Continuous Time Linear Equalizer)는 6.25 GHz에서 -21 dB 손실을 갖는 채널의 길게 늘어지는 ISI(Inter Symbol Interference)를 제거한다. 45 nm CMOS 공정을 이용하여 eye diagram에서 200 mV의 전압 마진과 0.75 UI의 시간 마진을 갖고 0.87 mW/Gb/s의 낮은 전력 소모를 유지한다.

This paper describes a 12.5 Gb/s low-power receiver design with equalizer adaptation. The receiver adapts to channel and chip process variation by adaptation circuit using sampler and serializer. The adaptation principle is explained. It describes technique receiving ground referenced differential signal of voltage-mode transmitter for low-power. The CTLE(Continuous Time Linear Equalizer) having 17.6 dB peaking gain to remove long tail ISI caused channel with -21 dB attenuation. The voltage margin is 210 mV and the timing margin is 0.75 UI in eye diagram. The receiver consumes 0.87 mW/Gb/s low power in 45 nm CMOS technology.

키워드

참고문헌

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