Transactions on Electrical and Electronic Materials

  • 제14권6호
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  • Pages.304-307
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  • 2013
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  • 1229-7607(pISSN)
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  • 2092-7592(eISSN)
한국전기전자재료학회 (The Korean Institute of Electrical and Electronic Material Engineers)
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Optimization of Reverse Engineering Processes for Cu Interconnected Devices

  • 투고 : 2013.08.05
  • 심사 : 2013.10.14
  • 발행 : 2013.12.25
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초록

Reverse engineering of semiconductor devices utilizes delayering processes, in order to identify how the interconnection lines are stacked over transistor gates. Cu metal has been used in recent fabrication technologies, and de-processes becomes more difficult with the shrinking device dimensions. In this article, reverse engineering technologies to reveal the Cu interconnection lines and Cu via-plugs embedded in dielectric layers are investigated. Stacked dielectric layers are removed by $CF_4$ plasma etching, then the exposed planar Cu metal lines and via-plugs are selectively delineated by wet chemical solution, instead of the commonly used plasma-based dry etch. As a result, we have been successful in extracting the layouts of multiple layers within a system IC, and this technique can be applicable to other logic IC, analog IC, and CMOS IC, etc.

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참고문헌

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