한국산업정보학회논문지 (Journal of Korea Society of Industrial Information Systems)

한국산업정보학회 (Korea Society of Industrial Information Systems)
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나노 MOSFET 공정에서의 초저전압 NCL 회로 설계

Design of Ultra Low-Voltage NCL Circuits in Nanoscale MOSFET Technology

  • 홍우헌 (대구대학교 전자공학과) ;
  • 김경기 (대구대학교 전자전기공학부)
  • 투고 : 2012.04.26
  • 심사 : 2012.08.09
  • 발행 : 2012.08.30
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초록

초저전력 설계나 에너지 수확 활용은 동적 전력과 정적 전력 사이의 균형을 이루는 점에 근접하는 문턱전압이하의 매우 낮은 전압에서 작동하는 디지털 시스템을 요구한다. 이런 동작 모드에서 일반적인 논리회로의 지연 변화는 매우 크게 된다. 따라서, 본 논문에서 MOSFET 나노 공정기술에서 전력소비를 줄이면서 여러 가지 공정 변이의 영향을 받지 않는 비동기 방식의 NCL (Null conventional logic)을 사용한 저전력 논리회로 설계 방법을 제안하고자 한다. 제안된 NCL 회로는 45nm의 공정기술에서 0.4V의 공급전압을 사용하였고, 각 NCL회로는 속도와 전력에 의해서 일반적인 동기식 회로와 비교되었다.

Ultra low-power design and energy harvesting applications require digital systems to operate under extremely low voltages approaching the point of balance between dynamic and static power consumption which is attained in the sub-threshold operation mode. Delay variations are extremely large in this mode. Therefore, in this paper, a new low-power logic design methodology using asynchronous NCL circuits is proposed to reduce power consumption and not to be affected by various technology variations in nanoscale MOSFET technology. The proposed NCL is evaluated using various benchmark circuits at 0.4V supply voltage, which are designed using 45nm MOSFET predictive technology model. The simulation results are compared to those of conventional synchrouns logic circuits in terms of power consumption and speed.

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참고문헌

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피인용 문헌

  1. Design and Implementation of Low power ALU based on NCL (Null Convention Logic) vol.18, pp.5, 2013, https://doi.org/10.9723/jksiis.2013.18.5.059
  2. A new interfacing circuit for low power asynchronous design in sensor systems vol.19, pp.1, 2014, https://doi.org/10.9723/jksiis.2014.19.1.061
  3. Delay Insensitive Asynchronous Circuit Design Based on New High-Speed NCL Cells vol.19, pp.6, 2014, https://doi.org/10.9723/jksiis.2014.19.6.001