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Design of eFuse OTP Memory Programmable in the Post-Package State for PMICs

Post-Package 프로그램이 가능한 eFuse OTP 메모리 설계

  • Received : 2012.06.11
  • Accepted : 2012.06.29
  • Published : 2012.08.31

Abstract

In this paper, we propose a FSOURCE circuit which requires such a small switching current that an eFuse OTP memory can be programmed in the post-package state of the PMIC chips using a single power supply. The proposed FSOURCE circuit removes its short-circuit current by using a non-overlapped clock and reduces its maximum current by reducing the turned-on slope of its driving transistor. Also, we propose a DOUT buffer circuit initializing the output data of the eFuse OTP memory with arbitrary data during the power-on reset mode. We design a 24-bit differential paired eFuse OTP memory which uses Magnachip's $0.35{\mu}m$ BCD process, and the layout size is $381.575{\mu}m{\times}354.375{\mu}m$($=0.135mm^2$).

본 논문에서는 단일전원을 사용하는 PMIC 칩이 패키지 상태에서 eFuse OTP 메모리를 프로그램 가능하도록 스위칭 전류가 작은 FSOURCE 회로를 제안하였다. 제안된 FSOURCE 회로는 non-overlapped clock을 사용하여 short-circuit current를 제거하였으며, 구동 트랜지스터의 ON되는 기울기를 줄여 최대 전류를 줄였다. 그리고 power-on reset 모드동안 eFuse OTP의 출력 데이터를 임의의 데이터로 초기화시키는 DOUT 버퍼 회로를 제안하였다. $0.35{\mu}m$ BCD 공정을 이용하여 설계된 24비트 differential paired eFuse OTP 메모리의 레이아웃 면적은 $381.575{\mu}m{\times}354.375{\mu}m$($=0.135mm^2$)이다.

Keywords

References

  1. H. K. Cha, I. H. Yun, J. B. Kim, B. C. So, K.H. Chun, I. K. Nam, and K. R. Lee, "A 32-KB standard CMOS antifuse one-time programmable ROM embedded in a 16-bit microcontroller", IEEE Journal of Solid-State Circuits, vol. 41, no. 9, Sep. 2006.
  2. S. H. KULKARNI. "High-density 3-Dmetal-fuse PROM featuring 1.37${\mu}m2$ 1T1R bit cell in 32nm high-k metal-gate CMOS technology", Symposium on VLSI Circuits, USA: IEEE Press, pp. 28-29, Jun. 2009.
  3. J. Fellner, P. Boesmueller, and H. Retter. "Lifetime study for a poly fuse in a 0.35 mm polycide CMOS process", Proceedings of the 43rd IEEE Annual International Reliability Physics Symposium. San Jose, pp. 446−449, 2005.
  4. C. Kpthandaraman, S. K. Iyer, and S. S. Iyer. "Electrically programmable fuse (eFuse) using electromigration in silicides", IEEE Electron Device Letters, vol. 23, no. 9, pp. 523-525, 2002. https://doi.org/10.1109/LED.2002.802657
  5. 김정호 외, "저전력 OTP Memory IP 설계 및 측정", 한국해양정보통신학회논문지, vol. 14, no. 11, Nov. 2010. https://doi.org/10.6109/jkiice.2010.14.11.2541
  6. Y. B. Park, I. H. Choi, D. H. Lee, L. Jin, J. H. Jang, P. B. Ha, Y. H. Kim, "Design of an eFuse OTP memory of 8 bits based on a 0.35um BCD process", Proceeding of 2011 International Conference on Mobile.IT Convergence, pp. 137-139. Sep. 2011.

Cited by

  1. 저잡음 · 고신뢰성 Differential Paired eFuse OTP 메모리 설계 vol.17, pp.10, 2012, https://doi.org/10.6109/jkiice.2013.17.10.2359