References
- S. Garg and D. Marculescu, "3D-GCP: An Analytical Model for the Impact of Process Variations on the Critical Path Delay Distribution of 3D ICs," in Proceedings of the 10th IEEE International Symposium on Quality Electronic Design, pp.147-155, Mar., 2009.
- S. Reda, A. Si, and R. I. Bahar, "Reducing the Leakage and Timing Variability of 2D ICs Using 3D ICs," in Proceedings of the 14th ACM/IEEE International Symposium on Low Power Electronics and Design, pp.283-286, Aug., 2009.
- S. Ozdemir, Y. Pan, A. Das, G. Memik, G. Loh, and A. Choudhary, "Quantifying and Coping with Parametric Variations in 3D-Stacked Microarchitectures," in Proceedings of the 47th ACM/IEEE Design Automation Conference, pp.144-149, Jun., 2010.
- M. Mondal and et al., "Thermally Robust Clocking Scheme for 3D Integrated Circuits," in Proceedings of the Conference on Design, Automation and Test in Europe, pp.1206-1211, Apr., 2007.
- V. Arunachalam and W. Burleson, "Low-Power Clock Distribution in a Multilayer Core 3D Microprocessor," in Proceedings of the 18th ACM Great Lakes Symposium on VLSI pp.429-434, May., 2008,.
- V. F. Pavlidis, I. Savidis, and E. G. Friedman, "Clock Distribution Networks for 3-D Integrated Circuits," in Proceedings of the IEEE 2008 Custom Integrated Circuits Conference pp.651-654, Sep., 2008,.
- J. Minz, X. Zhao, and S. K. Lim, "Buffered Clock Tree Synthesis for 3D ICs under Thermal Variations," in Proceedings of the 13th IEEE Asia and South Pacific Design Automation Conference, pp.504-509, Jan., 2008.
- X. Zhao, J. Minz, and S. K. Lim, "Low-Power and Reliable Clock Network Design for Through- Silicon Via (TSV) based 3D ICs," IEEE Transactions on Components, Packaging and Manufacturing Technology, Vol.1, No.2, pp.247-259, 2011. https://doi.org/10.1109/TCPMT.2010.2099590
- T.-Y. Kim and T. Kim, "Clock Tree Synthesis for TSV based 3D IC Designs," ACM Transactions on Design Automation of Electronic Systems, Vol.16, No.4, pp.48:1-48:21, 2011.
- T.-Y. Kim and T. Kim, "Bounded Skew Clock Routing for 3D Stacked IC Designs: Enabling Trade-offs between Power and Clock Skew," in Proceedings of the IEEE 2010 International Green Computing Conference, pp.525-532, Aug., 2010.
- X. Zhao, D. L. Lewis, h.-H. S. Lee, and S. K. Lim, "Low-Power Clock Tree Design for Pre-bond Testing of 3-D Stacked ICs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.30, No.5, pp.732-745, 2011. https://doi.org/10.1109/TCAD.2010.2098130
- T.-Y. Kim and T. Kim, "Clock Tree Synthesis with Pre-bond Testability for 3D Stacked IC Designs," in Proceedings of the 47th ACM/IEEE Design Automation Conference, pp.723-728, Jun., 2010.
- H. Xu, V. F. Pavlidis, and G. D. Micheli, "Process- Induced Skew Variation for Scaled 2-D and 3-D ICs," in Proceedings of the 12th ACM/IEEE International Workshop on System Level Interconnect Prediction, pp.17-24, Jun., 2010.
- J.-S. Yang, J. Pak, X. Zhao, S. K. Kim, and D. Z. Pan, "Robust Clock Tree Synthesis with Timing Yield Optimization for 3D-ICs," in Proceedings of the 16th IEEE Asia and South Pacific Design Automation Conference, pp.621-626, Jan., 2011.
- T.-Y. Kim and T. Kim, "On-Package Variation and Body Biasing Analysis on 3D Clock Tree," In Proceedings of the 26th International Technical Conference on Circuits/Systems, Computers, and Communications, pp.199-202, Jun., 2011.
- G. Smith, L. Smith, S. Hosali, and S. Arkalgud, "Yield Consideration in the Choice of 3D Technology," in Proceedings of the 2007 International Symposium on Semiconductor Manufacturing, pp.1-3, Oct., 2007.
- S. Reda, G. Smith, and L. Smith, "Maximizing the Functional Yield of Wafer-to-Wafer 3-D Integration," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.17, No.9, pp.1357-1362, 2009. https://doi.org/10.1109/TVLSI.2008.2003513
- C. Ferri, S. Reda, and R. I. Bahar, "Parametric Yield Management for 3D ICs: Models and Strategies for Improvement," ACM Journal on Emerging Technologies in Computing Systems, Vol.4, No.4, pp.19:1-19:22, 2008.
- B. Choi and Y. Shin, "Lookup Table-based Adaptive Body Biasing of Multiple Macros for Process Variation Compensation and Low Leakage," Journal of Circuits, Systems, and Computers, Vol.19, No.7, pp.1449-1464, 2010. https://doi.org/10.1142/S021812661000675X
- J. Y. Choi and et al., "Design Techniques to Minimize the Yield Loss for General Purpose ASIC/SoC Devices," in Proceedings of the IEEE 2009 International SoC Design Conferecne, pp.45- 48, Nov., 2009.
- J. Jeong, T. Izuka, T. Nakura, M. Ikeda, and K. Asada, "All-Digital PMOS and NMOS Process Variability Monitor Utilizing Buffer Ring with Pulse Counter," in Proceedings of the 16th IEEE Asia and South Pacific Design Automation Conference, pp.79-80, Jan., 2011.
- X. Zhang, K. Ishida, M. Takamiya, and T. Sakurai, "An On-Chip Characterizing System for Within- Die Delay Variation Measurement of Individual Standard Cells in 65-nm CMOS," in Proceedings of the 16th IEEE Asia and South Pacific Design Automation Conference, 109-110, Jan., 2011.
- H. W. Kuhn, "The Hungarian Method for the Assignment Problem," Naval Research Logistic Quarterly, Vol.2, pp.83-97, 1955. https://doi.org/10.1002/nav.3800020109
- C. H. Papadimitriou and K. Steiglitz, Combinatorial Optimization: Algorithms and Complexity, Dover Publications, 1998.
- M. Edahiro, "A Clustering-based Optimization Algorithm in Zero-Skew routings," in Proceedings of the 30th ACM/IEEE Design Automation Conference, 1993, pp.612-616.
- T.-H. Chao, Y.-C. Hsu, J.-M. Ho, K. D. Boese, and A. B. Kahng, "Zero-Skew Clock Routing with Minimum Wirelength," IEEE Transactions on Circuits and Systems, Vol.39, No.11, pp.799-814, 1992. https://doi.org/10.1109/82.204128
- ISPD, "ISPD 2009 Clock Network Synthesis Contest, http://ispd.cc/contests/09/ispd09cts.html," 2009.
- NCSU, "FreePDK, http://www.eda.ncsu.edu/wiki/FreePDK/".
- PTM, "Predictive Technology Model, http://ptm.asu.edu/".
Cited by
- Tier Adaptive Body Biasing: A Post-Silicon Tuning Method to Minimize Clock Skew Variations in 3-D ICs vol.3, pp.10, 2013, https://doi.org/10.1109/TCPMT.2013.2238581