마이크로전자및패키징학회지 (Journal of the Microelectronics and Packaging Society)

  • 제19권3호
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  • Pages.9-14
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  • 2012
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  • 1226-9360(pISSN)
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  • 2287-7525(eISSN)
한국마이크로전자및패키징학회 (The Korean Microelectronics and Packaging Society)
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전력전달 및 분배 향상을 위한 Interconnect 공정 기술

Interconnect Process Technology for High Power Delivery and Distribution

  • 오경환 (서울과학기술대학교 글로벌융합산업공학과) ;
  • 마준성 (서울과학기술대학교 NID융합기술대학원) ;
  • 김성동 (서울과학기술대학교 기계시스템디자인공학과) ;
  • 김사라은경 (서울과학기술대학교 NID융합기술대학원)
  • 투고 : 2012.08.30
  • 심사 : 2012.09.11
  • 발행 : 2012.09.30
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초록

전자 소자의 기술이 발달함에 따라 전력은 증가하고, 전압은 낮아지고, 입출력 범프 수가 증가하는 반면, 범프 피치는 크게 줄어들지 못하기 때문에 전력전달과 분배 문제는 점점 심각해지고 있다. 그동안 전력전달 문제를 해결하기 위해선 대부분 회로나 아키텍처 차원에서 에너지를 적게 소모하는 방법을 주로 연구해 왔으나, 최근 회로분야와 동시에 새로운 공정설계를 통해서 전력전달 및 분배를 높이고 발열 문제도 처리하는 interconnect 공정 기술이 중요시 되고 있다.

Robust power delivery and distribution are considered one of the major challenges in electronic devices today. As a technology develops (i.e. frequency and complexity, increase and size decreases), both power density and power supply noise increase, and voltage supply margin decreases. In addition, thermal problem is induced due to high power and poor power distribution. Until now most of studies to improve power delivery and distribution have been focused on device circuit or system architecture designs. Interconnect process technologies to resolve power delivery issues have not greatly been explored so far, but recently it becomes of great interest as power increases and voltage specification decreases in a smaller chip size.

키워드

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피인용 문헌

  1. Development of Cu CMP process for Cu-to-Cu wafer stacking vol.20, pp.4, 2013, https://doi.org/10.6117/kmeps.2013.20.4.081
  2. Characterization of flip chip bonded structure with Cu ABL power bumps vol.54, pp.8, 2014, https://doi.org/10.1016/j.microrel.2014.03.022