마이크로전자및패키징학회지 (Journal of the Microelectronics and Packaging Society)

  • 제19권3호
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  • Pages.1-7
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  • 2012
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  • 1226-9360(pISSN)
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  • 2287-7525(eISSN)
한국마이크로전자및패키징학회 (The Korean Microelectronics and Packaging Society)
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PCB 및 패키징 공정에서의 도금 시뮬레이션 기술 적용

Application of Plating Simulation for PCB and Pakaging Process

  • 이규환 (한국기계연구원 부설 재료연구소 표면기술연구본부)
  • 투고 : 2012.08.30
  • 심사 : 2012.09.07
  • 발행 : 2012.09.30
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초록

Electroplating technology is widely used in semiconductor microelectronic industry. With the development of semiconductor integrated circuit to high density and light-small scale, Extremely high quality and plated uniformity of the deposited metals are needed. Simulation technique can help to obtain better plating results. Although a few plating simulation softwares have been commercialized, plating simulation is not widely prevalent in Korea. In this paper, principle of electroplating and mathematical modeling of plating simulation are discussed. Also introduced are some cases enhancing plating thickness uniformity on leadframe, PCB and wafer by using plating simulation.

키워드

참고문헌

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피인용 문헌

  1. 전해 Cr/Ni-P 도금막의 열 사이클 신뢰성 및 균열거동 분석 vol.26, pp.4, 2012, https://doi.org/10.6117/kmeps.2019.26.4.133
  2. Development of a New Modeling Technique to Simulate 3-dimensional Electroplating System Considering the Effects of Fluid Flow vol.10, pp.4, 2012, https://doi.org/10.33961/jecst.2019.02894