참고문헌
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C.-M. Hsu, M.Z. Straayer, and M.H. Perrott, "A Low-Noise, Wide-BW 3.6-GHz Digital
$\Delta\Sigma$ Fractional-N Synthesizer with a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation," IEEE J. Solid-State Circuits, vol. 43, no. 12, Dec. 2008, pp. 2776-2786. https://doi.org/10.1109/JSSC.2008.2005704 - V. Kratyuk et al., "A Digital PLL with a Stochastic Time-to- Digital Converter," IEEE Trans. Circuits Syst. I, vol. 56, no. 8, Aug. 2009, pp. 1612-1621. https://doi.org/10.1109/TCSI.2008.2010109
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