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Low-Power, All Digital Phase-Locked Loop with a Wide-Range, High Resolution TDC

  • Pu, Young-Gun (Department of Electronic Engineering, Konkuk University) ;
  • Park, An-Soo (Department of Electronic Engineering, Konkuk University) ;
  • Park, Joon-Sung (Department of Electronic Engineering, Konkuk University) ;
  • Lee, Kang-Yoon (Department of Electronic Engineering, Konkuk University)
  • Received : 2010.05.22
  • Accepted : 2010.08.02
  • Published : 2011.06.30
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Abstract

In this paper, we propose a low-power all-digital phase-locked loop (ADPLL) with a wide input range and a high resolution time-to-digital converter (TDC). The resolution of the proposed TDC is improved by using a phase-interpolator and the time amplifier. The phase noise of the proposed ADPLL is improved by using a fine resolution digitally controlled oscillator (DCO) with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. The die area of the ADPLL is 0.8 $mm^2$ using 0.13 ${\mu}m$ CMOS technology. The frequency resolution of the TDC is 1 ps. The DCO tuning range is 58% at 2.4 GHz and the effective DCO frequency resolution is 0.14 kHz. The phase noise of the ADPLL output at 2.4 GHz is -120.5 dBc/Hz with a 1 MHz offset. The total power consumption of the ADPLL is 12 mW from a 1.2 V supply voltage.

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References

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