전기학회논문지P (The Transactions of the Korean Institute of Electrical Engineers P)

  • 제60권3호
  • /
  • Pages.126-132
  • /
  • 2011
  • /
  • 1229-800X(pISSN)
  • /
  • 2586-7792(eISSN)
대한전기학회 (The Korean Institute of Electrical Engineers)
권호 표지
DOI QR코드

DOI QR Code

정착시간과 레귤레이션 특성을 개선한 LDO(Low Dropout Regulator)의 설계

A Design of LDO(Low Dropout Regulator) with Enhanced Settling Time and Regulation Property

  • 박경수 (한양대 공대 전자컴퓨터통신공학과) ;
  • 박재근 (한양대 공대 전자컴퓨터통신공학과)
  • 투고 : 2011.07.05
  • 심사 : 2011.08.23
  • 발행 : 2011.09.01
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

A conventional LDO(Low Dropout Regulator) uses one OPAMP and one signal path. This means that OPAMP's DC Gain and Bandwidth can't optimize simultaneously within usable power. This also appears that regulation property and settling time of LDO can't improve at the same time. Based on this idea, a proposed LDO uses two OPAMP and has two signal path. To improve regulation property, OPAMP where is used in the path which qualities DC gain on a large scale, bandwidth designed narrowly. To improve settling time, OPAMP where is used in the path which qualities DC gain small, bandwidth designed widely. A designed LDO used 0.5um 1P2M process and provided 200mA of output current. A line regulation and load regulation is 12.6mV/V, 0.25mV/mA, respectively. And measured settling time is 1.5us in 5V supply voltage.

키워드

참고문헌

  1. F. Goodenough, "Off-line and one-cell IC converters up efficiency," Electron. Design, pp. 55-64, June 27, 1994.
  2. T. Regan, "Low dropout linear regulators improve automotive and battery-powered systems," Powerconversion Intell. Motion, pp. 65-69, Feb. 1990.
  3. G. A. Rincon-Mora and P. E. Allen, "A Low-voltage, Low Quiescent Current, Low Drop-out Regulator," IEEE J. Solid-State Circuits, vol. 33, Issue 1, pp. 36-44. Jan. 1998. https://doi.org/10.1109/4.654935
  4. G. A. Rincon-Mora and P. E. Allen, "Optimized Frequency-Shaping Circuit Topologies for LDO's," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 45, Issue 6, pp. 703-708. Jun. 1998. https://doi.org/10.1109/82.686689
  5. H. Banba, H. Shiga, A. Umezawa, T. Miyaba, T. Tanzawa, S. Atsumi, and K. Sakui, "A CMOS bandgap reference circuit with sub-1-V operation," IEEE J. Solid-State Circuits, vol.34, Issue 5, pp.670-674, 1999. https://doi.org/10.1109/4.760378
  6. Behzad Razavi, "Design of Analog CMOS Integrated Circuits," Mcgraw-Hill, pp.88-89, 2001.
  7. R. Hogervorst, J. P. Tero, R. G. H. Eschauzier, and J. H. Huijsing, "A compact power-efficient 3 V CMOS rail-to-rail input/output operational amplifier for VLSI cell libraries," IEEE J. Solid-State Circuits, vol. 29, Issue. 12, pp. 1505-1513, Dec. 1994. https://doi.org/10.1109/4.340424
  8. R. Hogervorst, J. H. Huijsing, "Design of Low-Voltage, Low-Power Operational Amplifier Cells," Kluwer Academic Publishers, pp.65-87, 1996.
  9. Bhupendra K. Ahuja, "An improved frequency compensation technique for cmos operational amplifiers," IEEE J. Solid-State Circuits, vol.18, Issue 6, pp.629-633, 1983. https://doi.org/10.1109/JSSC.1983.1052012
  10. Mehrmanesh, S.; Vahidfar, M.B.; Aslanzadeh, H.A.; Atarodi, M. "A 1-volt, high PSRR, CMOS bandgap voltage reference," Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium. on, vol. 1, pp. I-381-I384, May. 2003.
  11. G. A. Rincon-Mora, "A CMOS low dropout regulator stable with any load capacitor," TENCON 2004. 2004 IEEE Region 10 Conference, vol. D, Issue 21-24, pp. 26-32. Nov. 2004.