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Common Expression Extraction Using Two-cube Quotient Matrices

2-큐브 몫 행렬을 이용한 공통식 산출

  • Kwon, Oh-Hyeong (Division of Electroinc, Computer, and Communication, Hanseo University)
  • 권오형 (한서대학교 전자컴퓨터통신학부)
  • Received : 2011.07.14
  • Accepted : 2011.08.11
  • Published : 2011.08.31

Abstract

This paper presents a new Boolean extraction technique for logic synthesis. This method first calculates divisor/2-cube quotients, 2-cube quotient pairs, and 2-cube quotient matrices. Then we find candidates, which can be common sub-expressions, from 2-cube quotients and matrices. Next, candidate intersection provides the common sub-expressions for several logic expressions. Experimental results show the improvements in literal counts over the previous methods.

본 논문에서는 논리합성을 위한 부울 공통식 추출 방법을 제안한다. 제안하는 방법은 주어진 각 논리식들에서 제수/2-큐브 몫들과 2-큐브 몫 쌍들을 산출하고, 이들을 이용해서 2-큐브 몫 행렬을 만든다. 2-큐브 몫들과 행렬로부터 후보식들을 찾고, 다음 이 후보식들의 교집합에 의해 여러 논리식에서 사용되는 공통식을 산출한다. 실험 결과 제안하는 방법은 기존의 방법들보다 전체 논리식의 리터럴 개수를 줄일 수 있었다.

Keywords

References

  1. R. K. Brayton and C. McMullen, "The Decomposition and Factorization of Boolean Epressions." Proc. ISCAS, pp. 49-54, 1982.
  2. R. K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. R. Wang, " MIS: A Multiple-Level Logic Optimization System." IEEE Trans. CAD, Vol. 6, No. 6, pp. 1062-1081, 1987. https://doi.org/10.1109/TCAD.1987.1270347
  3. E. M. Sentovich, K. J. Singh, C. Moon, H. Savoj, R. K. Brayton, R. K., and A. Sangiovanni-Vincentelli, "Sequential Circuit Design Using Synthesis and Optimization." Proc. ICCD, pp. 328-333, 1992.
  4. J. Rajski and J. Vasudevamurthy, "The testabilitypreserving concurrent decomposition and factorization of Boolean expressions," IEEE Trans. CAD, Vol. 11, No. 6, pp. 778-79, 1992. https://doi.org/10.1109/43.137523
  5. V. K. Singh and A. A. Diwan, "Heuristic for decomposition in multilevel logic optimization," IEEE Trans. VLSI, Vol. 1, No. 4, pp. 441-445, 1993. https://doi.org/10.1109/92.250191
  6. W.-J. Hsu and W.-Z. Shen, "Coalgebraic division for multilevel logic synthesis," Proc. of DAC, pp. 438-442, 1992.
  7. C. Yang and M. Ciesielski, "BDS: A Boolean BDD-Based Logic Optimization System," IEEE Trans. CAD, Vol. 21, No. 7, pp. 866-876, 2002 https://doi.org/10.1109/TCAD.2002.1013899
  8. D. Wu and J. Zhu, "FBDD: A Folded Logic Synthesis System," Proc. of International Conference on ASIC(ASICON), pp. 746-751, 2005.
  9. D. Wu and J. Zhu, "BDD-based Two Variable Sharing Extraction," Proc. of Asia and South Pacific Design Automation Conference(ASPDAC), pp. 1031-1034, 2005.
  10. O.-H. Kwon, "Common Expression Extraction Using Kernel-Kernel pairs" Journal of the Korea Academiaindustrial cooperation Society, to be published. https://doi.org/10.5762/KAIS.2011.12.7.3251
  11. O.-H. Kwon, B. T. Chun, "Boolean Factorization Using Two-cube Non-kernels," Journal of the Korea Academia -industrial cooperation Society, Vol. 11, No. 11, pp. 4597-4603, 2010. https://doi.org/10.5762/KAIS.2010.11.11.4597
  12. IWLS 2005 Benchmarks, http://iwls.org/iwls2005/benchmarks.html