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솔더 인터커넥터를 이용한 3차원 TSV 패키지의 신뢰성 연구

Reliability Study of 3D TSV Package Using Solder Interconnect

  • 이행수 (울산과학대학 디지털 기계학부) ;
  • 김경호 (서울과학기술대학교 NID융합기술대학원) ;
  • 좌성훈 (서울과학기술대학교 NID융합기술대학원)
  • 발행 : 2011.06.30

초록

키워드

참고문헌

  1. Seungmin Hyun and Changwoo Lee : TSV Core Technology for 3D IC Packaging, Journal of KWS, 27-3 (2009), 4-9 (in Korea) https://doi.org/10.5781/KWJS.2009.27.3.004
  2. Sehoon Yoo and Chang-woo Lee : Through Silicon Via Filling and Fine Pitch Joining Technology for 3D Electronic Package, Journal of KWS, 27-3 (2009), 17-22 (in Korea) https://doi.org/10.5781/KWJS.2009.27.3.017
  3. M.C. Hsieh and C. K. Yu: Thermo-mechanical Simulations For 4-Layer StackedIC Packages, EuroSimE Conf., (2008) 1-7
  4. J. Zhang, Max O. Bloomfield, J. Lu, R. J. Gutmann, and T. S. Cale : Modeling Thermal Stresses in 3-D IC Interwafer Interconnects, IEEE Transactions on Semiconductor Manufacturing, 19-4 (2006) 437-448 https://doi.org/10.1109/TSM.2006.883587
  5. C. S. Selvanayagam, J. H. Lau, X. Zhang, S. Seah, K. Vaidyanathan and T. C. Chai : Nonlinear thermal stress/strain analyses of copper filled TSV and their flip-chip microbumps, 2008 Electronic Components and Technology Conference, (2008) 1073-1081
  6. L. J. Ladani : Numerical analysis of thermo- mechanical reliability of through silicon vias (TSVs) and solder interconnects in 3-dimensional integrated circuits, Microelectronic Eng., Vol. 87, (2010) 208-215 https://doi.org/10.1016/j.mee.2009.07.022
  7. K H. Lu, X. Zhang, S. Ryu, J. Im, R. Huang, and P. S. Ho : Thermo-Mechanical Reliability of 3-D ICs containing Through Silicon Vias, 2009 Electronic Components and Technology Conference, 630-634 https://doi.org/10.1109/ECTC.2009.5074079