Journal of Electrical Engineering and Technology

The Korean Institute of Electrical Engineers (대한전기학회)
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Compact Design of the Advanced Encryption Standard Algorithm for IEEE 802.15.4 Devices

  • Song, Oh-Young (School of Electrical and Electronic Engineering, Chung-Ang University) ;
  • Kim, Ji-Ho (School of Electrical and Electronic Engineering, Chung-Ang University)
  • Received : 2010.08.16
  • Accepted : 2010.12.30
  • Published : 2011.05.02
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Abstract

For low-power sensor networks, a compact design of advanced encryption standard (AES) algorithm is needed. A very small AES core for ZigBee devices that accelerates computation in AES algorithms is proposed in this paper. The proposed AES core requires only one S-Box, which plays a major role in the optimization. It consumes less power than other block-wide and folded architectures because it uses fewer logic gates. The results show that the proposed design significantly decreases power dissipation; however, the resulting increased clock cycles for 128-bit block data processing are reasonable for IEEE 802.15.4 standard throughputs.

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References

  1. Y. Xiao, et al., “MAC Security and Security Overhead Analysis in the IEEE 802.15.4 Wireless Sensor Networks,” EURASIP Journal on Wireless Communications and Networking, 2006, p. 1-12
  2. A. Dandalis, et al.: ‘A Comparative Study of Performance of AES Final Candidates Using FPGAs’, Lecture Notes in Computer Science, 2000, 1965, p. 133-153
  3. P. Chodowiec, et al., “Very compact FPGA implementation of the AES algorithm,” Lecture Notes in Computer Science, 2003, 2779, p. 319-333 https://doi.org/10.1007/978-3-540-45238-6_26
  4. M. Feldhofer, et al., “AES implementation on a grain of sand,” IEE Proc. Inf. Secur., 2005, 152, (1), p. 13-20 https://doi.org/10.1049/ip-ifs:20055006
  5. P. Hämäläinen, et al., “Design and implementation of low-area and low-power AES encryption hardware core,” 9th Euromicro Conf. on Digital System Design, 2006, p. 577-583
  6. Wireless Medium Access Control and Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area Networks (LRWPAN), IEEE Std. 802.15.4, 2006.
  7. Altera website, http://www.altera.com, 2008.
  8. S.J. Park, “Analysis of AES Hardware Implementations”, Department of Electrical and Computer Engineering, Oregon State University, 2003
  9. A. Satoh, et al., “A Compact Rijndael Hardware Architecture with S-Box Optimization”, Theory and Application of Cryptology and Information Security (ASIACRYPT 2001), Gold Coast, Australia, 2001
  10. S. Morioka, et al., “An Optimized S-Box Circuit Architecture for Low Power AES Design”, Cryptographic Hardware and Embedded Systems (CHES 2002), San Francisco Bay, CA, 2002.
  11. Advanced Encryption Standard (AES), FIPS Std. 197, 2001.

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