대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
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Intrinsic Cylindrical/Surrounding Gate SOI MOSFET의 I-V 특성 도출을 위한 해석적 모델

Analytical Model for Deriving the I-V Characteristics of an Intrinsic Cylindrical Surrounding Gate MOSFET

  • 우상수 (홍익대학교 전자전기공학부) ;
  • 이재빈 (홍익대학교 전자전기공학부) ;
  • 서정하 (홍익대학교 전자전기공학부)
  • Woo, Sang-Su (School of Electronic & Electrical Eng., Hongik Univ.) ;
  • Lee, Jae-Bin (School of Electronic & Electrical Eng., Hongik Univ.) ;
  • Suh, Chung-Ha (School of Electronic & Electrical Eng., Hongik Univ.)
  • 투고 : 2011.03.16
  • 심사 : 2011.10.21
  • 발행 : 2011.10.25
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초록

본 논문에서는 intrinsic-body cylindrical/surrounding gate SOI MOSFET의 I-V 특성 도출을 위한 간단한 해석적 모델을 제시하였다. Intrinsic 실리콘 채널 영역에서의 Poisson 방정식과 gate oxide 내에서의 Laplace 방정식을 해석적으로 풀어 소스와 드레인 양단 끝에서의 표면 전위 분포를 bisection method를 이용하여 구하였다. 구해진 표면 전위를 바탕으로 closed-form의 I-V 특성 식을 도출하였다. 도출된 I-V 특성 표현 식을 모의 실험한 결과, 소자의 parameter와 가해진 bias 전압에 대한 비교적 정확한 의존성을 확인할 수 있었다.

In this paper, a simple analytical model for deriving the I-V characteristics of a cylindrical surrounding gate SOI MOSFET with intrinsic silicon core is suggested. The Poisson equation in the intrinsic silicon core and the Laplace equation in the gate oxide layer are solved analytically. The surface potentials at both source and drain ends are obtained by means of the bisection method. From them, the surface potential distribution is used to describe the I-V characteristics in a closed-form. Simulation results seem to show the dependencies of the I-V characteristics on the various device parameters and applied bias voltages within a range of satisfactory accuracy.

키워드

참고문헌

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